topic Re: Can not get KL27 current draw down to expected values (in VLPS mode). in Kinetis Microcontrollers

Can not get KL27 current draw down to expected values (in VLPS mode).

rickstuart — Wed, 25 Mar 2015 15:12:00 GMT

Hi,

I am messing with various KL27 low current modes on the Freescale FRDM-KL27Z development board. Right now I want to:

1. Turn off the 48MHz clock.

2. Turn on the 2MHz clock.

3. Route the 2MHz clock to TPM0 timer.

4. Enter VLPS mode.

5. Draw 100uA or less (really was expecting less than half that).

6. Get woken up by the TPM0 timer interrupt.

However, step 5 is drawing 187uA!!

(Note, the processor is waking up about every 3 seconds, flashes the RGB LED on the FRDM-KL27Z development board then goes back to VLPS mode. So the program is doing what I want.)

The current value for the 2MHz clock can be found in Freescale document KL27P64M48SF2.pdf. There in table 10 it states the typical value is 25uA for turning on the 2MHz clock.

Now here is what I don't understand:

When I turn off the 2MHz internal reference clock the current drops by about 181uA!

To do this, I change this line of code:

MCG->C1 |= MCG_C1_IRCLKEN_MASK;

// LIRC is enabled.

To this:

///

MCG->C1 |= MCG_C1_IRCLKEN_MASK;

// LIRC is enabled.

Now the TPM0 interrupt does not occur (no surprise there) and the current draw while in VLPS mode is down from 181uA to 5.2uA! Way more than what I expected based on the 25uA allotment in the Freescale KL27P64M48SF2.pdf document. I suspect there is something else running off the LIRC (8MHz/2MHz) clock that I don't see or need. But I haven't found the culprit - if there is one. Does anyone have any candidates I could chase down?

-thanks

Re: Can not get KL27 current draw down to expected values (in VLPS mode).

rickstuart — Wed, 25 Mar 2015 19:05:39 GMT

This is interesting. During testing at a different clock rate (48MHz) involving no low power mode, I noticed that the processor current demand had nearly doubled from previous tests. The only code difference added the ability to monitor the processor clock on an external pin. Essentially, adding this clock monitoring pin cost us about 4mA taking us from about 4 to about 8mA.

So the thinking was to remove the clock monitoring pin and re-test processor current demand for the VLPS mode with a 2MHz clock connected to TPM0 to create timed wake up interrupts. That fix it! The processor current demand while in VLPS w/the above configuration dropped from 187uA to 19.2uA.

Driving the clock monitoring pin took an unexpected amount of current. If anyone can explain why it would be a great way to sum up this thread.

-thanks

Re: Can not get KL27 current draw down to expected values (in VLPS mode).

apanecatl — Wed, 25 Mar 2015 19:44:37 GMT

Sounds abnormally high, I will look into this and see what comes up, thanks for the heads up!!!

Re: Can not get KL27 current draw down to expected values (in VLPS mode).

rickstuart — Wed, 25 Mar 2015 21:21:36 GMT

At this point I should probably add that I have tomb-stoned the zero ohm resistors R23 and R22 on my FRDM-KL27Z board. Apparently the complete FRDM-KL27Z schematic is hard to come by. But according to what I am seeing these needed to be disconnected to prevent the accelerometer chip and the KL27 processor pin PTC3 (CLKOUTA) from back driving each other. Who knows, maybe there's still something hanging off pin 46 of the KL27 processor that we don't know about.

-thanks

Re: Re: Can not get KL27 current draw down to expected values (in VLPS mode).

rickstuart — Thu, 26 Mar 2015 14:58:44 GMT

We found that the scope probes were (significantly) contributing to the processor current demand. The new values are not as dramatic as before:

Processor Current Demands:
	w/scope probe	w/o scope probe	clock switch off from inside KL27 processor
48MHz	8.2mA	5.88mA	3.85mA
8MHz	698uA	394uA	107.1uA
2MHz	187uA	108uA	18uA

The data collected across different frequencies used different low power modes. So going up and down the table is not suggested. However, the power modes were consistent when moving across the table. So the relation of processor current demand verses test configuration should be (is assumed to be) good.

So, while the values are a bit more palatable, the question remains if the change in processor current demand is with in the expected limits for driving an external pin with the processor clock?

-thanks