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    <title>topic Re: Kinetis K10 MCU in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-MCU/m-p/328960#M15251</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1&amp;gt;&amp;nbsp; internal SRAM access speed is based on system clock(core clock).&lt;/P&gt;&lt;P&gt;2&amp;gt;&amp;nbsp; Cache is another memory range separated from SRAM. There is no conflict to using both cache and SRAM.&lt;/P&gt;&lt;P&gt;The code can run at Flash or SRAM.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Wish it helps.&lt;BR /&gt;best regards &lt;BR /&gt;Ma Hui&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 01 Aug 2014 01:45:54 GMT</pubDate>
    <dc:creator>Hui_Ma</dc:creator>
    <dc:date>2014-08-01T01:45:54Z</dc:date>
    <item>
      <title>Kinetis K10 MCU</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-MCU/m-p/328959#M15250</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am going through K10 sub-family reference manual. I need some of information.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. What is speed of internal RAM ?&lt;/P&gt;&lt;P&gt;2. I see there is cache memory. So if my code is running from RAM can I still use cache memory ? or the code has to run from FLASH memory ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Jul 2014 20:41:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-MCU/m-p/328959#M15250</guid>
      <dc:creator>prakashpatel</dc:creator>
      <dc:date>2014-07-31T20:41:40Z</dc:date>
    </item>
    <item>
      <title>Re: Kinetis K10 MCU</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-MCU/m-p/328960#M15251</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1&amp;gt;&amp;nbsp; internal SRAM access speed is based on system clock(core clock).&lt;/P&gt;&lt;P&gt;2&amp;gt;&amp;nbsp; Cache is another memory range separated from SRAM. There is no conflict to using both cache and SRAM.&lt;/P&gt;&lt;P&gt;The code can run at Flash or SRAM.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Wish it helps.&lt;BR /&gt;best regards &lt;BR /&gt;Ma Hui&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 01 Aug 2014 01:45:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-MCU/m-p/328960#M15251</guid>
      <dc:creator>Hui_Ma</dc:creator>
      <dc:date>2014-08-01T01:45:54Z</dc:date>
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