topic FlexBus Timing Diagrams in Kinetis Microcontrollers

FlexBus Timing Diagrams

gcary — Fri, 29 Aug 2014 17:34:07 GMT

In the documentation for the K60, FB_TS and FB_ALE are shown as indeterminate at the beginning of the cycle. Why is this? I assume there must be a reason why it has been drawn it this way, and I need to understand why in order to design a reliable FlexBus interface.

I have only seen two instances of the diagram being drawn as I expect it should be. In AN4393, Figures 10 and 11 show FB_ALE as I think it should be. Every other diagram I've seen shows the signal as indeterminate at the start of the cycle.

Regards,

Greg

Re: FlexBus Timing Diagrams

Kan_Li — Mon, 01 Sep 2014 08:12:28 GMT

Hi Gcary，

I am contacting the validation Owner for flexbus module, and will let you know when I have any more information.

Thanks for your patience!

Best Regards,

Kan

Re: FlexBus Timing Diagrams

Kan_Li — Mon, 01 Sep 2014 08:17:54 GMT

Hi Gcary,

I have just got the feedback, the figure 10 and 11 in AN4393 is correct, the undetermined end means another transfer can start, and the undetermined beggining in the RM should be a typo, the defaul stat for ALE is low, and for TS it is high.

Hope that makes sense,

Have a great day,
B.R
Kan

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Re: FlexBus Timing Diagrams

gcary — Mon, 01 Sep 2014 18:11:35 GMT

Thank you very much Kan for confirming my thoughts. I needed to make sure I wasn't overlooking something.

Best Regards,

Greg