How to output I2S0_RX_FS in master mode?

cfgmgr — Thu, 28 Jun 2012 23:00:41 GMT

Device: MK60DN512ZVDM10 - mask 0M33Z

I'm struggling a bit to understand how to output an I2S RX frame clock signal out of the K60's PTE8/I2S0_RX_FS pin.

Here's the setup: I have a Cirrus Logic CS42488 audio chip that I am attempting to run in TDM slave mode, with the K60 supplying all the clocks to the audio chip (MCLK, LRCK, SCLK). I wish to receive 8 channels of audio from this chip in TDM mode. For this application, I don't need to output any audio to this chip - just receive from it. The chip needs 12.288 Mhz MCLK and SCLK, and a LRCK clock at 48kHz.

I am successful in outputting the MCLK & SCLK (12.288 Mhz) from the K60, but I cannot seem to get the I2S0_RX_FS clock to output anything. By experimenting with different configurations, I am able to get the TX section (which I don't need) to output a frame clock on I2S0_TX_FS pin, but I cannot seem to output anyting on the I2S0_RX_FS pin.

I am running the I2S system as a network master, in synchronous mode, using the MUX(4) standard configuration for all the I2S pins.

Does anyone have any examples of code that drives the I2S0_RX_FS pin as an output? Or am I approaching this design incorrectly? Do I just need to wire the I2S0_TX_FS pin to the audio chip's LRCK? Or am I completely missing the boat here?

Confused...

Re: How to output I2S0_RX_FS in master mode?

cfgmgr — Thu, 28 Jun 2012 23:57:41 GMT

I figured it out (all it takes is an embarrasing post to the forum!)

I should not have been running in "synchronous" mode. If I had read the manual more carefully, I would have noticed that synchronous mode share a common STCK and STFS port.... Clearing the SYN bit in I2S0_CR solved teh problem.

Sorry to bother you all...

topic How to output I2S0_RX_FS in master mode? in Kinetis Microcontrollers

How to output I2S0_RX_FS in master mode?

Re: How to output I2S0_RX_FS in master mode?