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    <title>topic Is there a Kinetis ID register? in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Is-there-a-Kinetis-ID-register/m-p/292845#M11822</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;How can the CPU model be identified? I found a generic ARM core identification register here: &lt;A href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439d/Cihhbddh.html" title="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439d/Cihhbddh.html"&gt;ARM Information Center&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a Freescale-specific ID somewhere, which identifies the particular Kinetis model, maskset, etc.?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 21 Nov 2013 22:03:57 GMT</pubDate>
    <dc:creator>alipoth</dc:creator>
    <dc:date>2013-11-21T22:03:57Z</dc:date>
    <item>
      <title>Is there a Kinetis ID register?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Is-there-a-Kinetis-ID-register/m-p/292845#M11822</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;How can the CPU model be identified? I found a generic ARM core identification register here: &lt;A href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439d/Cihhbddh.html" title="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439d/Cihhbddh.html"&gt;ARM Information Center&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a Freescale-specific ID somewhere, which identifies the particular Kinetis model, maskset, etc.?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Nov 2013 22:03:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Is-there-a-Kinetis-ID-register/m-p/292845#M11822</guid>
      <dc:creator>alipoth</dc:creator>
      <dc:date>2013-11-21T22:03:57Z</dc:date>
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    <item>
      <title>Re: Is there a Kinetis ID register?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Is-there-a-Kinetis-ID-register/m-p/292846#M11823</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Andras&lt;/P&gt;&lt;P&gt;There is a register in Kinetis for chip identification, called SIM_SDID.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope my reply can help you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Paul&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Nov 2013 00:46:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Is-there-a-Kinetis-ID-register/m-p/292846#M11823</guid>
      <dc:creator>Paul_Tian</dc:creator>
      <dc:date>2013-11-22T00:46:45Z</dc:date>
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    <item>
      <title>Re: Is there a Kinetis ID register?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Is-there-a-Kinetis-ID-register/m-p/292847#M11824</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Incomplete snipped of code I use in my bootloader, that shows the registers that tell something about the part:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&amp;nbsp; data_u32&amp;nbsp; = (RCM_SRS0 &amp;lt;&amp;lt; 24UL);&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/TD&gt;&lt;TD&gt;/* System Reset Status Register 0 */&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;&amp;nbsp; data_u32 |= (RCM_SRS1 &amp;lt;&amp;lt; 16UL);&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/TD&gt;&lt;TD&gt;/* System Reset Status Register 1 */&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_RESET ] = data_u32;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_SDID&amp;nbsp; ] = SIM_SDID;&amp;nbsp; /* System Device Identification Register */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_FCFG1 ] = SIM_FCFG1; /* Flash Configuration Register 1 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_FCFG2 ] = SIM_FCFG2; /* Flash Configuration Register 2 */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_UIDHM ] = SIM_UIDMH; /* Unique Identification Register Mid-High */&lt;/P&gt;&lt;P&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_UIDML ] = SIM_UIDML; /* Unique Identification Register Mid Low&amp;nbsp; */&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_UIDL&amp;nbsp; ] = SIM_UIDL;&amp;nbsp; /* Unique Identification Register Low&amp;nbsp; &lt;/TD&gt;&lt;TD&gt;*/&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; sys_id_adr_u32[ SYS_DEV_ID_COMPC ] = SIM_COPC;&amp;nbsp; /* COP Control Register */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;....&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* 00000002 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_SDID ] &amp;amp; SIM_SDID_FAMID(0x07U))&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;gt;&amp;gt;&amp;nbsp; SIM_SDID_FAMID_SHIFT) );&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Kinetis family */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /*&amp;nbsp; 00000005 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_SDID ] &amp;amp; SIM_SDID_SUBFAMID(0x07U)) &amp;gt;&amp;gt;&amp;nbsp; SIM_SDID_SUBFAMID_SHIFT) );&amp;nbsp;&amp;nbsp; /* Kinetis sub-family */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /*&amp;nbsp; 00000001 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_SDID ] &amp;amp; SIM_SDID_SERIESID(0x07U)) &amp;gt;&amp;gt;&amp;nbsp; SIM_SDID_SERIESID_SHIFT) );&amp;nbsp;&amp;nbsp; /* Kinetis Series ID */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* 00000001 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_SDID ] &amp;amp; SIM_SDID_REVID(0x0F))&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;gt;&amp;gt;&amp;nbsp; SIM_SDID_REVID_SHIFT) );&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Revision ID */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* 00000009 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_SDID ] &amp;amp; SIM_SDID_DIEID(0x1F))&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;gt;&amp;gt;&amp;nbsp; SIM_SDID_DIEID_SHIFT) );&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Die ID */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* 00000006 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_SDID ] &amp;amp; SIM_SDID_PINID(0x0F))&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;gt;&amp;gt;&amp;nbsp; SIM_SDID_PINID_SHIFT) );&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Package size */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* 00000007 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uint32_t const fcfg1_pfsize = ((sys_id_u32[ SYS_DEV_ID_FCFG1 ] &amp;amp; SIM_FCFG1_PFSIZE(0x0F))&amp;nbsp;&amp;nbsp; &amp;gt;&amp;gt; SIM_FCFG1_PFSIZE_SHIFT);&amp;nbsp;&amp;nbsp;&amp;nbsp; /* P-flash size */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( fcfg1_pfsize );&amp;nbsp;&amp;nbsp;&amp;nbsp; /* P-flash size */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&amp;nbsp; pf_size_u32 = (1U &amp;lt;&amp;lt; (14U + (fcfg1_pfsize &amp;gt;&amp;gt; 1U))); /* Only valid for $3, $5, $7, $9, $B, $D */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( pf_size_u32 );&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* 00000010 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_FCFG2 ] &amp;amp; SIM_FCFG2_MAXADDR(0x7F))&amp;nbsp;&amp;nbsp; &amp;gt;&amp;gt; SIM_FCFG2_MAXADDR_SHIFT) );&amp;nbsp; /* Max address of flash */&lt;/P&gt;&lt;P&gt;&amp;nbsp; uart0_write_byte( (uint8_t) ' ' );&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* 00000005 */&lt;/P&gt;&lt;P&gt;&amp;nbsp; hex32( ((sys_id_u32[ SYS_DEV_ID_SDID ]&amp;nbsp; &amp;amp; SIM_SDID_SRAMSIZE(0x07U))&amp;nbsp; &amp;gt;&amp;gt;&amp;nbsp; SIM_SDID_SRAMSIZE_SHIFT) ); /* RAM Size */&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Nov 2013 15:19:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Is-there-a-Kinetis-ID-register/m-p/292847#M11824</guid>
      <dc:creator>bobpaddock</dc:creator>
      <dc:date>2013-11-22T15:19:09Z</dc:date>
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