GPIO Open Drain: Schematic?

belskyc — Tue, 12 Jul 2011 05:37:15 GMT

Hello,

In the Kinetis K60 uP, the general-purpose-input-output (GPIO) port register PORTx_PCRn, bit ODE called "Open Drain Enable" allows the port to be configured with an "Open Drain Output". Could anyone please explain to me what the significance of Open-Drain is? Schematically speaking, what does the port look like with the "Open Drain" enabled vs. disabled? I'm trying to understand when an application would want an Open-Drain output vs. a non-open-drain.

Thanks and regards,

Re: GPIO Open Drain: Schematic?

mjbcswitzerland — Wed, 13 Jul 2011 04:43:47 GMT

I think that a standard open-drain description contains this information:

http://en.wikipedia.org/wiki/Open_collector

Regards

Mark

topic Re: GPIO Open Drain: Schematic? in Kinetis Microcontrollers

GPIO Open Drain: Schematic?

Re: GPIO Open Drain: Schematic?