topic Re: K60 FlexBus in Kinetis Microcontrollers

K60 FlexBus

dporada — Tue, 23 Apr 2013 12:45:35 GMT

I'm trying to connect a 512k x 16bit sram chip to a TWR-K60D100M board using FlexBus. To do this, I need 19 address bits, 16 data bits, CS, R/W, OE and ALE. I am using a 74HC373 and latching A16, A17, and A18 with the ALE signal.

Here's the first question. When I am addressing the memory at any location, the A30 (D14) pin seems to be the same as the ALE signal. If I disable the ALE signal, the A30 signal is still there so it's not a short. I get this signal on the PRIMARY ELEVATOR board with only the TWR-K60D100M connected at pin B74. Any Ideas?

The second question is about using a 16 bit bus. When I try to write to an odd address, FlexBus writes to the odd and then the even address. If I write to the even address, there is only one write. Is this normal?

I tried looking at the TWR-MEM board since it uses a 16 bit memory chip, but it ties the upper and lower 8 bits together to make an 8 bit bus.

Thanks in advance for any help.

Re: K60 FlexBus

Hui_Ma — Sat, 27 Apr 2013 02:41:34 GMT

Hi Donald,

1> About TWR-K60D100M PTB21 pin status, customer need to check if set PORTB_PCR21 register [MUX] bits with ALT5 function.
I checked K60 100MHz Flexbus module validation report, there is no record info about Flexbus pin function with problem.

2> That performance is caused by Flexbus address misaligned transfer.

Thank you for the attention.

Re: K60 FlexBus

dporada — Sat, 27 Apr 2013 12:16:11 GMT

Here's the code. Most was copied from the app notes.

PORTC_PCR3 = (PORTC_PCR3 & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(1) ;

SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK; // Enable the clock to the FlexBus

SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x0); //FlexBus Clock not divided

// Set the GPIO ports clocks

SIM_SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |

SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;

PORTB_PCR20 = PORT_PCR_MUX(5); // fb_ad[31] used as d[15]

PORTB_PCR21 = PORT_PCR_MUX(5); // fb_ad[30] used as d[14]

PORTB_PCR22 = PORT_PCR_MUX(5); // fb_ad[29] used as d[13]

PORTB_PCR23 = PORT_PCR_MUX(5); // fb_ad[28] used as d[12]

PORTC_PCR12 = PORT_PCR_MUX(5); // fb_ad[27] used as d[11]

PORTC_PCR13 = PORT_PCR_MUX(5); // fb_ad[26] used as d[10]

PORTC_PCR14 = PORT_PCR_MUX(5); // fb_ad[25] used as d[9]

PORTC_PCR15 = PORT_PCR_MUX(5); // fb_ad[24] used as d[8]

PORTB_PCR6 = PORT_PCR_MUX(5); // fb_ad[23] used as d[7]

PORTB_PCR7 = PORT_PCR_MUX(5); // fb_ad[22] used as d[6]

PORTB_PCR8 = PORT_PCR_MUX(5); // fb_ad[21] used as d[5]

PORTB_PCR9 = PORT_PCR_MUX(5); // fb_ad[20] used as d[4]

PORTB_PCR10 = PORT_PCR_MUX(5); // fb_ad[19] used as d[3]

PORTB_PCR11 = PORT_PCR_MUX(5); // fb_ad[18] used as d[2]

PORTB_PCR16 = PORT_PCR_MUX(5); // fb_ad[17] used as d[1]

PORTB_PCR17 = PORT_PCR_MUX(5); // fb_ad[16] used as d[0]

PORTB_PCR18 = PORT_PCR_MUX(5); // fb_ad[15]

PORTC_PCR0 = PORT_PCR_MUX(5); // fb_ad[14]

PORTC_PCR1 = PORT_PCR_MUX(5); // fb_ad[13]

PORTC_PCR2 = PORT_PCR_MUX(5); // fb_ad[12]

PORTC_PCR4 = PORT_PCR_MUX(5); // fb_ad[11]

PORTC_PCR5 = PORT_PCR_MUX(5); // fb_ad[10]

PORTC_PCR6 = PORT_PCR_MUX(5); // fb_ad[9]

PORTC_PCR7 = PORT_PCR_MUX(5); // fb_ad[8]

PORTC_PCR8 = PORT_PCR_MUX(5); // fb_ad[7]

PORTC_PCR9 = PORT_PCR_MUX(5); // fb_ad[6]

PORTC_PCR10 = PORT_PCR_MUX(5); // fb_ad[5]

PORTD_PCR2 = PORT_PCR_MUX(5); // fb_ad[4]

PORTD_PCR3 = PORT_PCR_MUX(5); // fb_ad[3]

PORTD_PCR4 = PORT_PCR_MUX(5); // fb_ad[2]

PORTD_PCR5 = PORT_PCR_MUX(5); // fb_ad[1]

PORTD_PCR6 = PORT_PCR_MUX(5); // fb_ad[0]

PORTB_PCR19 = PORT_PCR_MUX(5); // fb_oe_b

PORTC_PCR11 = PORT_PCR_MUX(5); // fb_rw_b

PORTD_PCR1 = PORT_PCR_MUX(5); // fb_cs0_b

PORTD_PCR0 = PORT_PCR_MUX(5); // fb_ale

PORTC_PCR3 = PORT_PCR_MUX(5); // fb_clk

FB_CSCR0 = FB_CSCR_PS(0x02) // 16-bit port

| FB_CSCR_AA_MASK // auto-acknowledge

| FB_CSCR_WS(0x2) // 2 wait states

;

FB_CSMR0 = FB_CSMR_BAM(0xF) //Set base address mask for 1M address space

| FB_CSMR_V_MASK //Enable cs valid signal

;

FB_CSAR0 = (0x60000000); //Set Base address

Re: K60 FlexBus

Hui_Ma — Sun, 28 Apr 2013 03:09:35 GMT

I check your attached code about Flexbus clock:
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x0); //FlexBus Clock not divided

Just remind: customer need to make sure the Flexbus clock not exceed 50MHz.

If you want to access TWR-MEM MRAM memory, the port size is 8-bit.

Customer can refer Kinetis 100MHz flexbus example code for more detailed info:

FB_CSCR0 = FB_CSCR_PS(1) // 8-bit port

| FB_CSCR_AA_MASK // auto-acknowledge

| FB_CSCR_ASET(0x1) // assert chip select on second clock edge after address is asserted

| FB_CSCR_WS(0x1) // 1 wait state - may need a wait state depending on the bus speed

;

Wish it helps.