PortE on K32L3A6

darknight — Mon, 18 Jan 2021 17:53:21 GMT

Hi,

I test the FRDM-K32L3A6

in the file K32L3A60_cm4.h (under the folder device) there is on line 6992 to 7000

definition of PORTE, but if i understand the reference manual this port is only accessible for the

cortex m0+ core, so this definition can be removed ?

also in file pin_mux.h, there is

void BOARD_InitPins_cm4(void); /* Function assigned for the Cortex-M4F */

with definition for SW3 to SW5 connected to the portE, so this can be removed also.

Thanks

Best Regards

Re: PortE on K32L3A6

darknight — Fri, 22 Jan 2021 18:27:31 GMT

erratum, the cortex M4 can access port E, so all is good, just a configuration is missed from the sdk :

/* Clock Gate Control: Clock enabled. The current clock selection and divider options are locked. */
CLOCK_EnableClock(kCLOCK_Rgpio1); // this line must be add to access GPIO_BASE address
CLOCK_EnableClock(kCLOCK_PortE);// this line is generated from sdk or configtools

thanks to the support.

topic PortE on K32L3A6 in K32 L Series Microcontrollers

PortE on K32L3A6

Re: PortE on K32L3A6