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    <title>topic Re: Hard fault writing LPSPI0-&amp;gt;TDR in K32 L Series Microcontrollers</title>
    <link>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1643624#M125</link>
    <description>&lt;P&gt;Unless the function is an interrupt it should not be declared as naked.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 03 May 2023 13:20:58 GMT</pubDate>
    <dc:creator>bobpaddock</dc:creator>
    <dc:date>2023-05-03T13:20:58Z</dc:date>
    <item>
      <title>Hard fault writing LPSPI0-&gt;TDR</title>
      <link>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1640656#M122</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I try to write a function for a very small bootloader. Which should send commands to a display.&lt;/P&gt;&lt;P&gt;However the last statement "LPSPI0-&amp;gt;TDR = (uint32_t)(0x20&amp;lt;&amp;lt;8);" cause a hard fault and I dont know why. Can anyone help me? The MCU is a K32L2A31A.&lt;/P&gt;&lt;LI-CODE lang="c"&gt;__attribute__ ((naked, section(".after_vectors.reset")))
void showBLMInfo(void){

	//Connect CMP1 with TPM2
	TRGMUX_TPM2 = TRGMUX_TRGCFG_SEL0(0b100111);

	//Comparator for regulated Chargepump
	PCC_CMP1 = PCC_CLKCFG_CGC_MASK; //Clock enable
	//Caution Vin2 as reference is VDD, datasheet is wrong here!
	CMP1-&amp;gt;DACCR = CMP_DACCR_DACEN_MASK | CMP_DACCR_VRSEL_MASK | CMP_DACCR_VOSEL(0x2E);
	CMP1-&amp;gt;MUXCR = CMP_MUXCR_MSEL(7) | CMP_MUXCR_PSEL(0);
	CMP1-&amp;gt;CR1 = CMP_CR1_EN_MASK;

	//Generate PWM for Chargepump
	PCC_TPM2 = PCC_CLKCFG_CGC_MASK | PCC_CLKCFG_PCS(2); //Clock enable, Fast IRC
	TPM2-&amp;gt;CONF = TPM_CONF_CPOT_MASK | TPM_CONF_TRGSEL(0) | TPM_CONF_DBGMODE_MASK;
	TPM2-&amp;gt;CNT = 0;
	TPM2-&amp;gt;MOD = 10;
	TPM2-&amp;gt;CONTROLS[1].CnSC = TPM_CnSC_ELSB_MASK  | TPM_CnSC_MSB_MASK;
	TPM2-&amp;gt;CONTROLS[1].CnV = 5;

	//Enable Chargepump
	TPM2-&amp;gt;SC = TPM_SC_CMOD(1) | TPM_SC_PS(2);

	//GPIO
	//GPIO_SPI0_CS_DISP_GPIO-&amp;gt;PCOR = GPIO_SPI0_CS_DISP_GPIO_PIN_MASK;
	//EN_U_BAT, EN_DISP
	PCC_PORTE = PCC_CLKCFG_CGC_MASK; //Clock enable PORT E
	PCC_PORTD = PCC_CLKCFG_CGC_MASK; //Clock enable PORT D
	PORTE-&amp;gt;PCR[1] = PORT_PCR_MUX(1); //EN_U_BAT
	PORTE-&amp;gt;PCR[25] = PORT_PCR_MUX(2); //EN_DISP
	PORTD-&amp;gt;PCR[0] = PORT_PCR_MUX(2); //CS
	PORTD-&amp;gt;PCR[1] = PORT_PCR_MUX(2); //SCK
	PORTD-&amp;gt;PCR[2] = PORT_PCR_MUX(2); //MOSI
	GPIOE-&amp;gt;PDDR = (1U &amp;lt;&amp;lt; 25U) | (1U &amp;lt;&amp;lt; 1U);
	GPIOE-&amp;gt;PSOR = (1U &amp;lt;&amp;lt; 25U) | (1U &amp;lt;&amp;lt; 1U);

	//1Hz Refresh Clock
	//RTC-&amp;gt;CR |= RTC_CR_CPE(1);
	PCC_LPSPI0 = PCC_CLKCFG_CGC_MASK | PCC_CLKCFG_PCS(2); //Clock enable

	LPSPI0-&amp;gt;CR = LPSPI_CR_DBGEN_MASK | LPSPI_CR_MEN_MASK;
	LPSPI0-&amp;gt;CFGR1 = LPSPI_CFGR1_MASTER_MASK | LPSPI_CFGR1_PCSPOL(1) | LPSPI_CFGR1_AUTOPCS_MASK;
	LPSPI0-&amp;gt;CCR = LPSPI_CCR_PCSSCK(11)|LPSPI_CCR_SCKPCS(2)|LPSPI_CCR_DBT(4);

	//Send Display clear command
	LPSPI0-&amp;gt;TCR = LPSPI_TCR_FRAMESZ(15) | LPSPI_TCR_PRESCALE(4) | LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_CONT_MASK; //16bit Transfer
	LPSPI0-&amp;gt;TDR = (uint32_t)(0x20&amp;lt;&amp;lt;8);
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;Thanks a lot in advance.&lt;/P&gt;</description>
      <pubDate>Wed, 26 Apr 2023 14:03:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1640656#M122</guid>
      <dc:creator>nobodyKnows</dc:creator>
      <dc:date>2023-04-26T14:03:37Z</dc:date>
    </item>
    <item>
      <title>Re: Hard fault writing LPSPI0-&gt;TDR</title>
      <link>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1642041#M124</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;I found out the issue is not writing to "LPSPI0-&amp;gt;TDR". The issue is the return of the function. Why a return from a function cause a hard fault in startup code? The call stack looks good before the hardfault cause.&amp;nbsp; &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;I hope someone knows what is going on here.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Thanks a lot and best regards&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 06:48:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1642041#M124</guid>
      <dc:creator>nobodyKnows</dc:creator>
      <dc:date>2023-04-28T06:48:51Z</dc:date>
    </item>
    <item>
      <title>Re: Hard fault writing LPSPI0-&gt;TDR</title>
      <link>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1643624#M125</link>
      <description>&lt;P&gt;Unless the function is an interrupt it should not be declared as naked.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 03 May 2023 13:20:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1643624#M125</guid>
      <dc:creator>bobpaddock</dc:creator>
      <dc:date>2023-05-03T13:20:58Z</dc:date>
    </item>
    <item>
      <title>Re: Hard fault writing LPSPI0-&gt;TDR</title>
      <link>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1645381#M126</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;thanks a lot this was the solution. Just leave naked &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 05 May 2023 09:35:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/K32-L-Series-Microcontrollers/Hard-fault-writing-LPSPI0-gt-TDR/m-p/1645381#M126</guid>
      <dc:creator>nobodyKnows</dc:creator>
      <dc:date>2023-05-05T09:35:19Z</dc:date>
    </item>
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