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    <title>topic Re: NCache Region Overflow Error  in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/NCache-Region-Overflow-Error/m-p/1056739#M8224</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Omer,&lt;/P&gt;&lt;P&gt;It seems you put to much things in NCACHE_REGION. This region is at the end of SDRAM. You can enlarge its size.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Jing&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 03 Jul 2020 09:54:46 GMT</pubDate>
    <dc:creator>jingpan</dc:creator>
    <dc:date>2020-07-03T09:54:46Z</dc:date>
    <item>
      <title>NCache Region Overflow Error</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/NCache-Region-Overflow-Error/m-p/1056738#M8223</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hı ı am working on imxrt 1052 with custom board. Using Mcuxpresso 11.1.1 and&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;SDK_2.7.0_MIMXRT1052xxxxB . I encountered an error during debug session and ı can not understand what the problem is . I tried to optimize (properties -&amp;gt; setings -&amp;gt;MCU C compiler -&amp;gt; optimization -&amp;gt; optimization level -&amp;gt; optimize for size , optimize for debug (ı tried both))&amp;nbsp; but error messages not change, only the numberof bytes changed.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;void BOARD_ConfigMPU(void)&lt;BR /&gt;{&lt;BR /&gt;#if defined(__CC_ARM) || defined(__ARMCC_VERSION)&lt;BR /&gt; extern uint32_t Image$$RW_m_ncache$$Base[];&lt;BR /&gt; /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */&lt;BR /&gt; extern uint32_t Image$$RW_m_ncache_unused$$Base[];&lt;BR /&gt; extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];&lt;BR /&gt; uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;&lt;BR /&gt; uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?&lt;BR /&gt; 0 :&lt;BR /&gt; ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);&lt;BR /&gt;#elif defined(__MCUXPRESSO)&lt;BR /&gt; extern uint32_t __base_NCACHE_REGION;&lt;BR /&gt; extern uint32_t __top_NCACHE_REGION;&lt;BR /&gt; uint32_t nonCacheStart = (uint32_t)(&amp;amp;__base_NCACHE_REGION);&lt;BR /&gt; uint32_t size = (uint32_t)(&amp;amp;__top_NCACHE_REGION) - nonCacheStart;&lt;BR /&gt;#elif defined(__ICCARM__) || defined(__GNUC__)&lt;BR /&gt; extern uint32_t __NCACHE_REGION_START[];&lt;BR /&gt; extern uint32_t __NCACHE_REGION_SIZE[];&lt;BR /&gt; uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;&lt;BR /&gt; uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;&lt;BR /&gt;#endif&lt;BR /&gt; uint32_t i = 0;&lt;/P&gt;&lt;P&gt;/* Disable I cache and D cache */&lt;BR /&gt; if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk &amp;amp; SCB-&amp;gt;CCR))&lt;BR /&gt; {&lt;BR /&gt; SCB_DisableICache();&lt;BR /&gt; }&lt;BR /&gt; if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk &amp;amp; SCB-&amp;gt;CCR))&lt;BR /&gt; {&lt;BR /&gt; SCB_DisableDCache();&lt;BR /&gt; }&lt;/P&gt;&lt;P&gt;/* Disable MPU */&lt;BR /&gt; ARM_MPU_Disable();&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(0, 0x80000000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);&lt;/P&gt;&lt;P&gt;/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(1, 0x60000000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);&lt;/P&gt;&lt;P&gt;#if defined(XIP_EXTERNAL_FLASH) &amp;amp;&amp;amp; (XIP_EXTERNAL_FLASH == 1)&lt;BR /&gt; /* Region 2 setting: Memory with Normal type, not shareable, outer/inner write back. */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(2, 0x60000000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(3, 0x00000000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);&lt;/P&gt;&lt;P&gt;/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(4, 0x00000000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);&lt;/P&gt;&lt;P&gt;/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(5, 0x20000000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);&lt;/P&gt;&lt;P&gt;/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(6, 0x20200000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);&lt;/P&gt;&lt;P&gt;/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(7, 0x80000000U);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);&lt;/P&gt;&lt;P&gt;while ((size &amp;gt;&amp;gt; i) &amp;gt; 0x1U)&lt;BR /&gt; {&lt;BR /&gt; i++;&lt;BR /&gt; }&lt;/P&gt;&lt;P&gt;if (i != 0)&lt;BR /&gt; {&lt;BR /&gt; /* The MPU region size should be 2^N, 5&amp;lt;=N&amp;lt;=32, region base should be multiples of size. */&lt;BR /&gt; assert(!(nonCacheStart % size));&lt;BR /&gt; assert(size == (uint32_t)(1 &amp;lt;&amp;lt; i));&lt;BR /&gt; assert(i &amp;gt;= 5);&lt;/P&gt;&lt;P&gt;/* Region 8 setting: Memory with Normal type, not shareable, non-cacheable */&lt;BR /&gt; MPU-&amp;gt;RBAR = ARM_MPU_RBAR(8, nonCacheStart);&lt;BR /&gt; MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);&lt;BR /&gt; }&lt;/P&gt;&lt;P&gt;/* Enable MPU */&lt;BR /&gt; ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);&lt;/P&gt;&lt;P&gt;/* Enable I cache and D cache */&lt;BR /&gt; SCB_EnableDCache();&lt;BR /&gt; SCB_EnableICache();&lt;BR /&gt;}&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_5.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/114427iA1FA217C831642F2/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_5.png" alt="pastedImage_5.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_6.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/114428i1CC1777275C68545/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_6.png" alt="pastedImage_6.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_7.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/114429iCF44D8A41EBEF146/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_7.png" alt="pastedImage_7.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Jul 2020 09:53:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/NCache-Region-Overflow-Error/m-p/1056738#M8223</guid>
      <dc:creator>omerkaanbasakin</dc:creator>
      <dc:date>2020-07-02T09:53:06Z</dc:date>
    </item>
    <item>
      <title>Re: NCache Region Overflow Error</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/NCache-Region-Overflow-Error/m-p/1056739#M8224</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Omer,&lt;/P&gt;&lt;P&gt;It seems you put to much things in NCACHE_REGION. This region is at the end of SDRAM. You can enlarge its size.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Jing&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Jul 2020 09:54:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/NCache-Region-Overflow-Error/m-p/1056739#M8224</guid>
      <dc:creator>jingpan</dc:creator>
      <dc:date>2020-07-03T09:54:46Z</dc:date>
    </item>
    <item>
      <title>Re: NCache Region Overflow Error</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/NCache-Region-Overflow-Error/m-p/1056740#M8225</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/jingpan"&gt;jingpan&lt;/A&gt;‌,&lt;/P&gt;&lt;P&gt;Thanks for your reply.&amp;nbsp;&lt;/P&gt;&lt;P&gt;It seems solved the probelm&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Jul 2020 10:05:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/NCache-Region-Overflow-Error/m-p/1056740#M8225</guid>
      <dc:creator>omerkaanbasakin</dc:creator>
      <dc:date>2020-07-03T10:05:25Z</dc:date>
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