<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX RT Crossover MCUsのトピックWhat does the LPSPI transmit data zero-extend feature do for MSB first?</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/What-does-the-LPSPI-transmit-data-zero-extend-feature-do-for-MSB/m-p/1033539#M7301</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;the LPSPI Transmit Data Register TDR is built so that it zero-extends 8 and 16 bit writes&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/99757iDE97C74B7D5E0752/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;We want to fill the FIFO with DMA transfers. In case I have 5 bytes of data and a Framesize of 5 * 8 = 40 to send I will have one 4 byte DMA transfer and one 1 byte DMA transfer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The last DMA transfer will only write 8 bit to the register therefore the bits 8 to 31 will be zero.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;If the LPSPI module is set to MSB first will it send the zero data bits 24 to 31 instead of my expecet data?&lt;/LI&gt;&lt;LI&gt;If yes is it possible to write to bits 24 to 31 in TDR with DMA and will the lower bits automatically be 0 too?&lt;/LI&gt;&lt;LI&gt;Because of the limitation of DMA to 1,2 and 4 byte transfers it is not possible to send e.g. 3 bytes because I would have to write first 2 bytes to TDR (which will result in 2 zero bytes and 2 data bytes in TX FIFO) and then 1 byte (3 zero bytes in FIFO) which will result in at least 2 unwanted zero-bytes sent out through SPI right?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Stefan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 14 Feb 2020 14:41:47 GMT</pubDate>
    <dc:creator>imxrtuser</dc:creator>
    <dc:date>2020-02-14T14:41:47Z</dc:date>
    <item>
      <title>What does the LPSPI transmit data zero-extend feature do for MSB first?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/What-does-the-LPSPI-transmit-data-zero-extend-feature-do-for-MSB/m-p/1033539#M7301</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;the LPSPI Transmit Data Register TDR is built so that it zero-extends 8 and 16 bit writes&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/99757iDE97C74B7D5E0752/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;We want to fill the FIFO with DMA transfers. In case I have 5 bytes of data and a Framesize of 5 * 8 = 40 to send I will have one 4 byte DMA transfer and one 1 byte DMA transfer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The last DMA transfer will only write 8 bit to the register therefore the bits 8 to 31 will be zero.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;If the LPSPI module is set to MSB first will it send the zero data bits 24 to 31 instead of my expecet data?&lt;/LI&gt;&lt;LI&gt;If yes is it possible to write to bits 24 to 31 in TDR with DMA and will the lower bits automatically be 0 too?&lt;/LI&gt;&lt;LI&gt;Because of the limitation of DMA to 1,2 and 4 byte transfers it is not possible to send e.g. 3 bytes because I would have to write first 2 bytes to TDR (which will result in 2 zero bytes and 2 data bytes in TX FIFO) and then 1 byte (3 zero bytes in FIFO) which will result in at least 2 unwanted zero-bytes sent out through SPI right?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Stefan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Feb 2020 14:41:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/What-does-the-LPSPI-transmit-data-zero-extend-feature-do-for-MSB/m-p/1033539#M7301</guid>
      <dc:creator>imxrtuser</dc:creator>
      <dc:date>2020-02-14T14:41:47Z</dc:date>
    </item>
    <item>
      <title>Re: What does the LPSPI transmit data zero-extend feature do for MSB first?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/What-does-the-LPSPI-transmit-data-zero-extend-feature-do-for-MSB/m-p/1033540#M7302</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I did a test based on MCUXpresso SDK&amp;nbsp;interrupt_b2b_master demo.&lt;/P&gt;&lt;P&gt;I make below change with the code:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;uint32_t masterRxData[TRANSFER_SIZE] = {0U};&lt;/P&gt;&lt;P&gt;/*Master config*/&lt;BR /&gt; masterConfig.baudRate = TRANSFER_BAUDRATE;&lt;BR /&gt; masterConfig.bitsPerFrame = 40; //8;&lt;BR /&gt; masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;&lt;BR /&gt; masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;&lt;BR /&gt; masterConfig.direction = kLPSPI_MsbFirst;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;masterTxData[0] = 0x11223344;&lt;BR /&gt; masterTxData[1] = 0x55;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I could get below transfer siganl from captured scope:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/100868i4F20A408BD268DD8/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So,&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;the LPSPI module is set to MSB first it will send your expecet data.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Mike&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 18 Feb 2020 08:50:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/What-does-the-LPSPI-transmit-data-zero-extend-feature-do-for-MSB/m-p/1033540#M7302</guid>
      <dc:creator>Hui_Ma</dc:creator>
      <dc:date>2020-02-18T08:50:04Z</dc:date>
    </item>
    <item>
      <title>Re: What does the LPSPI transmit data zero-extend feature do for MSB first?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/What-does-the-LPSPI-transmit-data-zero-extend-feature-do-for-MSB/m-p/1033541#M7303</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for testing it Mike!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 18 Feb 2020 09:17:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/What-does-the-LPSPI-transmit-data-zero-extend-feature-do-for-MSB/m-p/1033541#M7303</guid>
      <dc:creator>imxrtuser</dc:creator>
      <dc:date>2020-02-18T09:17:44Z</dc:date>
    </item>
  </channel>
</rss>

