topic Re: About performance of SDRAM in IMXRT1050/60-EVK(B) in i.MX RT Crossover MCUs

About performance of SDRAM in IMXRT1050/60-EVK(B)

Takashi_Kashiwagi — Tue, 30 Oct 2018 15:40:25 GMT

Hello everyone,

I am hoping to use SDRAM somehow at high speed, but now it is very slow than TCM.

I measured performance of "Number of calls to vApplicationIdleHook per sec".

"vApplicationIdleHook" is as follows. This makes it possible to know how many times the vApplicationIdleHook was called in one second.

uint32_t g_u32CurrentRun = 0u;

DefKERNEL_SECTION_ITCM void vApplicationIdleHook(void)

{

uint32_t primask;

__asm volatile ("MRS %0, primask" : "=r" (primask) );

__asm volatile ("cpsid i" : : : "memory");

g_u32CurrentRun++;

__asm volatile ("MSR primask, %0" : : "r" (primask) : "memory");

}

other condition is as follows.
1. Kernel is on TCM.
2. Kernel is on SDRAM with chache
3. kernel is on SDRAM wtihout cache.

In all conditions, I used IMXRT1060-EVK with MCUXPresso IDE(GCC 7.2.1 20170904 (release) [ARM/embedded-7-branch revision 255204]) & -O2.

a result is as follows. (A larger number indicates a higher performance)

With TCM you get nearly maximum performance, but SDRAM is not far from that.

Is there any way to get SDRAM performance a bit more?

for reference, I atached projet File and xlsx.

We are looking forward to your advice.

T.Kashiwagi

Re: About performance of SDRAM in IMXRT1050/60-EVK(B)

art — Wed, 31 Oct 2018 09:12:02 GMT

The performance results you've collected look as the realistic ones. The reason is that TCM is accessed with the internal 64-bit wide AXI bus at core clock frequency, whereas SDRAM is accessed through the external (to the core) SEMC module on only 16-bit wide bus with lower clock frequency and higher latency. So, there seems to be no way to increase the code execution performance from SDRAM.

Have a great day,
Artur

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Re: About performance of SDRAM in IMXRT1050/60-EVK(B)

Takashi_Kashiwagi — Wed, 31 Oct 2018 12:14:42 GMT

Hi Petukhov

Thank you for the advice!!

> The reason is that TCM is accessed with the internal 64-bit wide AXI bus at core clock frequency, whereas SDRAM is accessed through the

> external (to the core) SEMC module on only 16-bit wide bus with lower clock frequency and higher latency.

I thought that it will be a little earlier because there is a cache, but I understood that it will not be earlier.

(I want the DDR 2 interface......)

Best Regards,

T.Kashiwagi