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    <title>i.MX RT Crossover MCUsのトピックRe: SAI MSB First Field</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974390#M4945</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN class=""&gt;&lt;A _jive_internal="true" data-content-finding="Community" data-userid="320108" data-username="amwilhite@indesign-llc.com" href="https://community.nxp.com/people/amwilhite@indesign-llc.com"&gt;Austin Wilhite&lt;/A&gt;&lt;/SPAN&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; You can check the RT reference manual about Figures 37-2 and 37-3, it means the Data in the FIFO can be aligned anywhere within the 32-bit wide register through the use of the First Bit Shifted configuration field, which selects the bit index (between 31 and 0) of the first bit shifted.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps you!&lt;/P&gt;&lt;P&gt;If you still have questions about it, please kindly let me know.&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Kerry&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 13 Nov 2019 01:48:17 GMT</pubDate>
    <dc:creator>kerryzhou</dc:creator>
    <dc:date>2019-11-13T01:48:17Z</dc:date>
    <item>
      <title>SAI MSB First Field</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974387#M4942</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I was hoping someone could explain the effect of the SAI MSB First (MF) field on the receipt of data via I2S.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In this case, does MSB still stand for most significant &lt;EM&gt;byte&lt;/EM&gt; (and not most significant &lt;EM&gt;bit&lt;/EM&gt;)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My interpretation is the following:&lt;/P&gt;&lt;P&gt;MSB First (MF) specifies if the first byte received per word is the most significant or least significant.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Example:&lt;/P&gt;&lt;P&gt;16-bit words&lt;/P&gt;&lt;P&gt;1111 0000 0000 1111 is shifted out, from left to right&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With the MSB First (MF) set to 1 (selecting MSB):&lt;/P&gt;&lt;P&gt;The sample value is 0xF00F&lt;/P&gt;&lt;P&gt;the receive buffer (in our little-endian system) reads:&lt;/P&gt;&lt;P&gt;Base Address: 0x0F&lt;/P&gt;&lt;P&gt;Base Address + 1: 0xF0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;With the&amp;nbsp;LSB&amp;nbsp;First (MF) set to 0 (selecting LSB):&lt;/P&gt;&lt;P&gt;The sample value is 0x0FF0&lt;/P&gt;&lt;P&gt;The receive buffer &lt;SPAN&gt;&amp;nbsp;(in our little-endian system)&amp;nbsp;&lt;/SPAN&gt;reads:&lt;/P&gt;&lt;P&gt;Base Address: 0xF0&lt;/P&gt;&lt;P&gt;Base Address + 1: 0x0F&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this correct?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Oct 2019 19:00:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974387#M4942</guid>
      <dc:creator>amwilhite</dc:creator>
      <dc:date>2019-10-28T19:00:47Z</dc:date>
    </item>
    <item>
      <title>Re: SAI MSB First Field</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974388#M4943</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" data-content-finding="Community" data-userid="320108" data-username="amwilhite@indesign-llc.com" href="https://community.nxp.com/people/amwilhite@indesign-llc.com"&gt;Austin Wilhite&lt;/A&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; After double check with our SAI expert, the MSB and LSB is significant &lt;EM&gt;bit&lt;/EM&gt;, not byte.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; The RT SAI in default is using LSB.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; When you use the FIFO aligned within the 32bit wide register, you need to refer to this Figure:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/93954iDAC0F1420A0BE6B7/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps you!&lt;/P&gt;&lt;P&gt;If you still have questions about it, please kindly let me know.&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Kerry&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Oct 2019 07:04:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974388#M4943</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2019-10-29T07:04:16Z</dc:date>
    </item>
    <item>
      <title>Re: SAI MSB First Field</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974389#M4944</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Kerry,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Although the&lt;SPAN style="color: #000000; background-color: #ffffff;"&gt;&amp;nbsp;RT SAI&amp;nbsp;registers default to&amp;nbsp;LSb, the SAI driver defaults to MSb.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you explain how to interpret Figures 37-2 and 37-3? It's not clear to me what exactly they are attempting to illustrate.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Nov 2019 14:05:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974389#M4944</guid>
      <dc:creator>amwilhite</dc:creator>
      <dc:date>2019-11-12T14:05:05Z</dc:date>
    </item>
    <item>
      <title>Re: SAI MSB First Field</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974390#M4945</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN class=""&gt;&lt;A _jive_internal="true" data-content-finding="Community" data-userid="320108" data-username="amwilhite@indesign-llc.com" href="https://community.nxp.com/people/amwilhite@indesign-llc.com"&gt;Austin Wilhite&lt;/A&gt;&lt;/SPAN&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; You can check the RT reference manual about Figures 37-2 and 37-3, it means the Data in the FIFO can be aligned anywhere within the 32-bit wide register through the use of the First Bit Shifted configuration field, which selects the bit index (between 31 and 0) of the first bit shifted.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps you!&lt;/P&gt;&lt;P&gt;If you still have questions about it, please kindly let me know.&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Kerry&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P style="min- padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt; Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Nov 2019 01:48:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/974390#M4945</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2019-11-13T01:48:17Z</dc:date>
    </item>
    <item>
      <title>Re: SAI MSB First Field</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/1345513#M16447</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Can you explain how to interpret Figures 37-2 and 37-3? It's not clear to me what exactly they are attempting to illustrate.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 24 Sep 2021 03:44:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SAI-MSB-First-Field/m-p/1345513#M16447</guid>
      <dc:creator>vdinh</dc:creator>
      <dc:date>2021-09-24T03:44:43Z</dc:date>
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