topic DMA and On Chip RAM in i.MX RT Crossover MCUs

DMA and On Chip RAM

Harjit — Tue, 22 Oct 2019 04:58:15 GMT

From reading AN12437, it seems that the DMA engine can access ITCM, DTCM and OCRAM. Is this true?

How does one deal with coherency i.e. let's say I have a buffer in DTCM or OCRAM and am DMAing data from the UART. Do I use the MPU to configure the region as non-cached?

I haven't found the document that talks about cache, DMA and coherency.

Thanks.

Re: DMA and On Chip RAM

Takashi_Kashiwagi — Wed, 23 Oct 2019 02:01:07 GMT

Hi Harjit-san

The following threads are helpful.

RT1060 - use of OCRAM breaks fatfs example

How does one deal with coherency i.e. let's say I have a buffer in DTCM or OCRAM and am DMAing data from the UART. Do I use the MPU to configure the region as non-cached?

Yes. Please set OCRAM to non-chached(shareble).

Please refer to the following document.

ARM Cortex-M7 Processor Technical Reference Manual – Memory Protection Unit

Best Regards,

T.Kashiwagi

Re: DMA and On Chip RAM

jeremyzhou — Thu, 24 Oct 2019 06:58:23 GMT

Hi Harjit Singh,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Is this true?
-- Yes.
1) Do I use the MPU to configure the region as non-cached?
-- Yes, it should do that.

Have a great day,
TIC

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