topic Re: i.MX RT 1052 in i.MX RT Crossover MCUs

i.MX RT 1052

zhangyanming — Fri, 08 Jun 2018 01:30:49 GMT

Lately，I test the i.MX RT 1052 chip，using the cortex-M7 kernel,I put the code in the Out of chip memory ，Program variable in the DTCM,when i test,I enable I-cache and D-cache,the algorithm test time is 14S. when I enable I-cache and disable D-cache,the algorithm test time is 109S,The kernel access to DTCM is not affected by the D-cache,but the test result is non-conformity ,so i want to get the answer,please.thank you.

Re: i.MX RT 1052

nxf46170 — Thu, 14 Jun 2018 21:50:15 GMT

Hello Zhang Yamming,

Cold you please clarify more information about your algorithm test?

Also, please describe what type of memory configuration you are running. By "out of chip memory", are you using Hyperflash, QSPI, etc.? Is this where you are loading the code onto?

When you refer to the "kernel", what exactly do you mean?

What methods are you taking to disable D-Cache? If you haven't already, please try to referring to the Application note found at the following link: https://www.nxp.com/docs/en/application-note/AN12042.pdf

Thank you for choosing NXP.

Let us know if you have any more questions.

Manuel, Jacob

Re: i.MX RT 1052

Yuri — Fri, 15 Jun 2018 05:47:27 GMT

Hello, zhangyanming

Looks like some settings are not fully correct in Your system, since DTCM/ITCM is

Tightly Coupled Memories, core can access it directly; cache is not involved.

Do you use the recent SDK?

Have a great day,

Yuri

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