<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Debug Port Inaccessible – MCU Issue, Not Boot in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Debug-Port-Inaccessible-MCU-Issue-Not-Boot/m-p/2329338#M36341</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/89955"&gt;@samjalkh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your interest in NXP MIMXRT series!&lt;/P&gt;
&lt;P&gt;Did this issue occur during the debugging phase after you accessed a specific register address? However, based on the log, this address appears to be an ENET peripheral register rather than one in OCRAM. If that's the case, the discussion in this post may be helpful to you:&amp;nbsp;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1575898" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1575898&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Gavin&lt;/P&gt;</description>
    <pubDate>Tue, 10 Mar 2026 02:14:50 GMT</pubDate>
    <dc:creator>Gavin_Jia</dc:creator>
    <dc:date>2026-03-10T02:14:50Z</dc:date>
    <item>
      <title>Debug Port Inaccessible – MCU Issue, Not Boot</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Debug-Port-Inaccessible-MCU-Issue-Not-Boot/m-p/2329020#M36337</link>
      <description>&lt;P&gt;&lt;SPAN&gt;I’d like to share a problem I encountered while working with the &lt;STRONG&gt;EVK-MIMXRT1024&lt;/STRONG&gt; board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;This is &lt;STRONG&gt;not a boot loader issue&lt;/STRONG&gt; – it’s an MU-level problem. When attempting to debug, I consistently get the following errors:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;15: Target error from Read Memory&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8004&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8008&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8010&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8014&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8024&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8040&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8044&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8064&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8084&lt;BR /&gt;Debug port inaccessible after access at location 0x402D80C4&lt;BR /&gt;Debug port inaccessible after access at location 0x402D80E4&lt;BR /&gt;Debug port inaccessible after access at location 0x402D80E8&lt;BR /&gt;Debug port inaccessible after access at location 0x402D80EC&lt;BR /&gt;Debug port inaccessible after access at location 0x402D80F0&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8100&lt;BR /&gt;Debug port inaccessible after access at location 0x402D8118&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;STRONG&gt;Debugging context:&lt;/STRONG&gt; evkmimxrt1024_hello_world Link Server Debug&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The debug port becomes inaccessible after memory access attempts at specific addresses in O CRAM. This strongly indicates an &lt;STRONG&gt;MU-side fault&lt;/STRONG&gt; rather than a boot loader misconfiguration&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 09 Mar 2026 13:59:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Debug-Port-Inaccessible-MCU-Issue-Not-Boot/m-p/2329020#M36337</guid>
      <dc:creator>samjalkh</dc:creator>
      <dc:date>2026-03-09T13:59:58Z</dc:date>
    </item>
    <item>
      <title>Re: Debug Port Inaccessible – MCU Issue, Not Boot</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Debug-Port-Inaccessible-MCU-Issue-Not-Boot/m-p/2329338#M36341</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/89955"&gt;@samjalkh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your interest in NXP MIMXRT series!&lt;/P&gt;
&lt;P&gt;Did this issue occur during the debugging phase after you accessed a specific register address? However, based on the log, this address appears to be an ENET peripheral register rather than one in OCRAM. If that's the case, the discussion in this post may be helpful to you:&amp;nbsp;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1575898" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1575898&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Gavin&lt;/P&gt;</description>
      <pubDate>Tue, 10 Mar 2026 02:14:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Debug-Port-Inaccessible-MCU-Issue-Not-Boot/m-p/2329338#M36341</guid>
      <dc:creator>Gavin_Jia</dc:creator>
      <dc:date>2026-03-10T02:14:50Z</dc:date>
    </item>
  </channel>
</rss>

