topic Ethernet clock issue in i.MX RT Crossover MCUs

Ethernet clock issue

Bhardwaj — Tue, 06 Jan 2026 06:03:26 GMT

Hi,

We have a custom board with imxrt1176 controller that is interfaced to 1G ethernet phy(DP83869).

Changed the configuration registers then it is working good and checked for 10mbps it is working fine but when we change the ethernet to 100mbps connection then it is not able to ping.

Then probed on all signals and identified that imxrt1176 is not generating 25mhz clock on Eth_tx_clk and it is continuous 2.5MHZ.

After searching a relevant document is found in that mentioned that we need to change clock to 125Mhz as shown in below figure:

As per the above screenshot modified clock in clock tool as shown in below figure:

Re: Ethernet clock issue

Gavin_Jia — Tue, 06 Jan 2026 07:49:35 GMT

Hi @Bhardwaj ,

Thanks for your interest in NXP MIMXRT series!

Have you successfully resolved this clock issue by following the instructions in AN14215?

Best regards,
Gavin

Re: Ethernet clock issue

Bhardwaj — Tue, 06 Jan 2026 08:21:35 GMT

Hi @Gavin_Jia ,

No, the issue is not solved. Another observation also found that when we change the speed to 1Gbps then the clock is changing to 25Mhz.

Re: Ethernet clock issue

Gavin_Jia — Thu, 08 Jan 2026 02:25:45 GMT

Hi @Bhardwaj ,

Thanks for the information.

I noticed you submitted the same ticket in SFDC. As we discussed, I suspect the clock you're monitoring originates from the PHY rather than the MAC. Please try the relevant GPR5 configuration and testing. Thanks in advance!

Best regards,
Gavin

Re: Ethernet clock issue

Bhardwaj — Thu, 22 Jan 2026 05:18:48 GMT

Hi @Gavin_Jia,

I had checked that but there are two GPR5 in clock_config.c

At line 875

/* Set ENET_1G Tx clock source. */

IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);

/* Set ENET_1G Ref clock source. */

IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;

At line 1697

/* Set ENET_1G Tx clock source. */

IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);

/* Set ENET_1G Ref clock source. */

IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;

Tried by removing line 1697-1700 still no change.

Modified the phy related functions. Attaching modified fsl_phyrtl8211f.c file please check.

why am unable to get 25Mhz on Tx_clk pin when rx_clk is 25mhz in 100mbps but when changed to 1gbps then tx_clk is getting 25mhz? ?