topic Synchronize Channels of Quad Timer on i.MX in i.MX RT Crossover MCUs

Synchronize Channels of Quad Timer on i.MX

aberger — Wed, 09 Jul 2025 17:00:15 GMT

It should be possible to synchronize multiple channels of a Quad Timer (TMR) module on the i.MX RT1050 by writing multiple bits to the TMRx_ENBL register (see Section 53.11.14 of the RM).

I am working with the SDK_2.x_EVKB_IMXRT1050. It only provides memory-mapped access to the TMR registers (via the `TMR_Type`) at the CHANNEL level, so an atomic write to the ENBL register to enable multiple channels simultaneously is not possible with the `TMR_Type` typedef.

As a concrete example, I would like to enable Channels 0 and 1 of TMR3 simultaneously. This should be possible with something like `TMR3->ENBL = 3U;`. I think that the current implementation, where ENBL is part of the CHANNEL struct (and so is accessed at 4 locations in the `TMR_Type` struct), is not arranged properly.

Re: Synchronize Channels of Quad Timer on i.MX

mayliu1 — Thu, 10 Jul 2025 07:52:38 GMT

Hi @aberger ,

Thank you so much for your interest in our products and for using our community.

Regarding "It should be possible to synchronize multiple channels of a Quad Timer (TMR) module on the i.MX RT1050 by writing multiple bits to the TMRx_ENBL register (see Section 53.11.14 of the RM)."

Yes, your understanding is correct, Multiple ENBL bits can be set at the same time to synchronize the start of separate counters.

As for “As a concrete example, I would like to enable Channels 0 and 1 of TMR3 simultaneously. This should be possible with something like `TMR3->ENBL = 3U;`. I think that the current implementation, where ENBL is part of the CHANNEL struct (and so is accessed at 4 locations in the `TMR_Type` struct), is not arranged properly.”

Please pay attention that TMRx_ENBL register default value is 1, it means 0001b - Timer channel is enabled. (default).

So if you want realize enable Channels 0 and 1 of TMR3 simultaneously, first, you need clear TMRx_ENBL(TMR3->ENBL = 0U ,disable Channels 0 and 1 ). After all the TMR configuration, then you can set `TMR3->ENBL = 3U.

The SDK provides basic drivers. However, if customers need to implement more complex driver functions, they can add the required code as needed.

Wish it helps you.
If you still have question about it, please kindly let me know.

Wish you a nice day!

Best Regards
MayLiu

Re: Synchronize Channels of Quad Timer on i.MX

aberger — Thu, 10 Jul 2025 22:15:53 GMT

Thank you @mayliu1. In general if issues or shortcomings are discovered with the SDK, is there a better place to report them (e.g. submit an issue to a GitHub repository)?

Re: Synchronize Channels of Quad Timer on i.MX

mayliu1 — Fri, 11 Jul 2025 06:14:12 GMT

Hi @aberger ,

Thanks for your updated information.

I will create an internal ticket to relevant NXP team for your inquire.

Thanks for your raising this question.

Best Regards

MayLiu