i.MX RT Crossover MCUsのトピックRe: RT1176 FlexSPI2 XIP + ROM Flash API

RT1176 FlexSPI2 XIP + ROM Flash API

gobbo — Sat, 08 Mar 2025 10:28:31 GMT

Hi,

we have a iMXRT1176 with a MX25UM1345 attached to FlexSPI2, from which we do XIP.

I have been following this guide and have adapted the fsl_romapi example code as instructed.

https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/RT1170-Octal-flash-enablement/ta-p/1498369

I *assume* FlexSPIInstance=2U is the correct value, but there is no documentation for this from what I can tell. Setting to 2U gives me a filled out nor config structure, so I assume this is correct. Furthermore, from single-stepping, I see that in the "cache clear" ROM API function call, we access 400D0000; which is the FlexSPI2 controller; and if i put in 1U we access 400CC000.

Do note that I run this code XIP; and I have set up the LUTS as shown in the tutorial.

A few differences appear.

1. I get 8 CMD and 8 Query pads back from the Getconfig call. This is strange to me, because we use the same chip as mentioned in the tutorial (" Successfully get FLEXSPI NOR configuration block with option_8bit").

2. I hang on Page Erase 4 out of 5 times (roughly).

I have a hunch that this is related to the AHB (xip) / IP command interaction on FlexSPI2 interface. I assume this is thoroughly tested though?

Re: RT1176 FlexSPI2 XIP + ROM Flash API

gobbo — Sat, 08 Mar 2025 10:31:46 GMT

Note, our flash is MX25UM51345GXDI00 and it's on the primary pin group for flexspi2.

Re: RT1176 FlexSPI2 XIP + ROM Flash API

gobbo — Sat, 08 Mar 2025 11:58:48 GMT

Hello,

I would like to add a couple of findings.

The first finding is obvious. Interrupts absolutely must be off when executing flash IP commands. This makes sense. We even store the interrupt vectors on the flash; so I can understand why this would cause problems.

Trick #1 then is

__asm("cpsid i");

... immediately at boot (for this instance -- so the plan is to generally disable it).

How-ever, this is strangely not insufficient to avoid hangs when erasing or writing. The second requirement, and this is where I am fully stumped; is to disable AHB prefetching on the FlexSPI module after calling the NOR Initialization code:

 status = ROM_FLEXSPI_NorFlash_Init(flexspi_instance, &g_nor_config);
// disable ahb prefetching here to avoid hangs
base->AHBCR |= FLEXSPI_AHBCR_PREFETCHEN_MASK;
base->AHBCR &= ~(FLEXSPI_AHBCR_PREFETCHEN_MASK);

... 
status = ROM_FLEXSPI_NorFlash_Erase(flexspi_instance, &g_nor_config, 0x0F0000, 4096);
...etc.

where base is just a pointer to FLEXSPI2 module interface.

So far I have re-run this code 10 times and it does not fail.

But this approach seems fragile; and I absolutely must understand *why* this works. I can get a vague sense of the problem; since FLEXSPI module will read more data and put it into AHB prefetch buffers, the IP commands interfering with this data somehow makes sense.

Is this a known errata?

Re: RT1176 FlexSPI2 XIP + ROM Flash API

Habib_MS — Tue, 11 Mar 2025 22:11:43 GMT

Hello @gobbo,
The last mentioned could be the issue, since the AHB and the IP commands share the CM7 bus:

So, there could be a collision between them.
BR
Habib.