<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Using SDRAM for large data on imxRT1050 EVKB in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1991292#M32527</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242788"&gt;@rajtend&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;How are you accessing the arrays? Are I tried to recreate the issue, but I am not able to; it works OK for me. I have the following arrays as global variables:&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;AT_NONCACHEABLE_SECTION_ALIGN(double arrA[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrA1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrB[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrB1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrC[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrC1[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrD[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrD1[100], 8);&lt;/LI-CODE&gt;
&lt;P&gt;And under main, I set a value of 8 to all of them at their last position:&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;    arrA[100] = 8;
    arrA1[100] = 8;
    arrB[100] = 8;
    arrB1[100] = 8;
    arrC[200] = 8;
    arrC1[200] = 8;
    arrD[100] = 8;
    arrD1[100] = 8;&lt;/LI-CODE&gt;
&lt;P&gt;This results in no compilation error or hard fault either.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Take a look into the following community post:&amp;nbsp;&lt;A href="https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Imprecise-Bus-Error-when-trying-to-make-use-of-SDRAM-on-RT1020/m-p/1561226" target="_blank"&gt;Solved: Re: Imprecise Bus Error when trying to make use of SDRAM on RT1020 EVK - NXP Community&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;As well as the following application note (specifically section "4.3.2. Use non-cacheable buffers"):&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12042.pdf" target="_blank"&gt;Using the i.MXRT L1 Cache&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;Edwin.&lt;/P&gt;</description>
    <pubDate>Fri, 08 Nov 2024 22:29:04 GMT</pubDate>
    <dc:creator>EdwinHz</dc:creator>
    <dc:date>2024-11-08T22:29:04Z</dc:date>
    <item>
      <title>Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1990428#M32509</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using iMXRT1050 EVKB.&lt;BR /&gt;I have an application which has large data arrays.&lt;BR /&gt;I cannot allocate them over heap or stack as the size is quite small.&lt;/P&gt;&lt;P&gt;When I tried to allocate the arrays in NCACHE region, then the application compiles.&lt;BR /&gt;However I get hard fault accessing the region.&lt;BR /&gt;How to solve this problem?&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;double&lt;/SPAN&gt;&lt;SPAN&gt; arrA[100], 8);&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt; arrA1[100], 8);&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;double&lt;/SPAN&gt;&lt;SPAN&gt; arrB[100], 8);&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt; arrB1[100], 8);&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;double&lt;/SPAN&gt;&lt;SPAN&gt; arrC[200], 8);&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt; arrC1[200], 8);&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;double&lt;/SPAN&gt; &lt;SPAN&gt;arrD&lt;/SPAN&gt;&lt;SPAN&gt;[100], 8);&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN&gt;AT_NONCACHEABLE_SECTION_ALIGN(&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt; arrD1[100], 8);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Linker configuration:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="rajtend_1-1731002407700.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/309275i04AB5AA5190FEAB5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="rajtend_1-1731002407700.png" alt="rajtend_1-1731002407700.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;Hard fault:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="rajtend_0-1731002160163.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/309274i476012B023EF2197/image-size/medium?v=v2&amp;amp;px=400" role="button" title="rajtend_0-1731002160163.png" alt="rajtend_0-1731002160163.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 07 Nov 2024 18:00:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1990428#M32509</guid>
      <dc:creator>rajtend</dc:creator>
      <dc:date>2024-11-07T18:00:15Z</dc:date>
    </item>
    <item>
      <title>Re: Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1990481#M32510</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242788"&gt;@rajtend&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Please make sure you follow the steps listed on the following blog post:&amp;nbsp;&lt;A href="https://mcuoneclipse.com/2021/05/26/placing-code-in-sections-with-managed-gnu-linker-scripts/" target="_blank"&gt;Placing Code in Sections with managed GNU Linker Scripts | MCU on Eclipse&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;Edwin.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 07 Nov 2024 19:46:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1990481#M32510</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2024-11-07T19:46:41Z</dc:date>
    </item>
    <item>
      <title>Re: Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1991142#M32520</link>
      <description>I have followed the steps, however the hard fault doesn't go away.</description>
      <pubDate>Fri, 08 Nov 2024 14:31:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1991142#M32520</guid>
      <dc:creator>rajtend</dc:creator>
      <dc:date>2024-11-08T14:31:54Z</dc:date>
    </item>
    <item>
      <title>Re: Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1991292#M32527</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242788"&gt;@rajtend&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;How are you accessing the arrays? Are I tried to recreate the issue, but I am not able to; it works OK for me. I have the following arrays as global variables:&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;AT_NONCACHEABLE_SECTION_ALIGN(double arrA[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrA1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrB[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrB1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrC[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrC1[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrD[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrD1[100], 8);&lt;/LI-CODE&gt;
&lt;P&gt;And under main, I set a value of 8 to all of them at their last position:&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;    arrA[100] = 8;
    arrA1[100] = 8;
    arrB[100] = 8;
    arrB1[100] = 8;
    arrC[200] = 8;
    arrC1[200] = 8;
    arrD[100] = 8;
    arrD1[100] = 8;&lt;/LI-CODE&gt;
&lt;P&gt;This results in no compilation error or hard fault either.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Take a look into the following community post:&amp;nbsp;&lt;A href="https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Imprecise-Bus-Error-when-trying-to-make-use-of-SDRAM-on-RT1020/m-p/1561226" target="_blank"&gt;Solved: Re: Imprecise Bus Error when trying to make use of SDRAM on RT1020 EVK - NXP Community&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;As well as the following application note (specifically section "4.3.2. Use non-cacheable buffers"):&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12042.pdf" target="_blank"&gt;Using the i.MXRT L1 Cache&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Fri, 08 Nov 2024 22:29:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1991292#M32527</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2024-11-08T22:29:04Z</dc:date>
    </item>
    <item>
      <title>Re: Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1991323#M32530</link>
      <description>Can you please tell me?&lt;BR /&gt;1. What is the starting address for SDRAM for imx RT1050 evkb? where can i find it?&lt;BR /&gt;2. What does the following code means? I saw it asserted in one time while running.&lt;BR /&gt;/* The MPU region size should be 2^N, 5&amp;lt;=N&amp;lt;=32, region base should be multiples of size. */&lt;BR /&gt;assert(!(nonCacheStart % size));&lt;BR /&gt;assert(size == (uint32_t)(1 &amp;lt;&amp;lt; i));</description>
      <pubDate>Fri, 08 Nov 2024 23:14:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1991323#M32530</guid>
      <dc:creator>rajtend</dc:creator>
      <dc:date>2024-11-08T23:14:37Z</dc:date>
    </item>
    <item>
      <title>Re: Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1992119#M32539</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242788"&gt;@rajtend&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;The available size for the RT1050 can be found on its Reference Manual, specifically on "Table 3-1. System memory map (CM7)":&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EdwinHz_0-1731342554755.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/309816iCC418B59D85DE79E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="EdwinHz_0-1731342554755.png" alt="EdwinHz_0-1731342554755.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The code you mention makes sure of two things: The first like asserts that the region base (nonCacheStart) is a multiple of size. The second makes sure that size is no larger than 2^32, since the variable 'i' will have the base-2 order of size due to the previous "while()":&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;    while ((size &amp;gt;&amp;gt; i) &amp;gt; 0x1U)
    {
        i++;
    }&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;If the code asserts and breaks at that point, it means that the MPU region size does not comply with the condition where it is a multiple of size, or that it is bigger than 2^32.&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Mon, 11 Nov 2024 16:52:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1992119#M32539</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2024-11-11T16:52:42Z</dc:date>
    </item>
    <item>
      <title>Re: Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1992174#M32540</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;&lt;BR /&gt;Thanks a lot for the steps.&lt;BR /&gt;I am able to make it work. I have added several preprocessor defines:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="rajtend_0-1731348658298.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/309828iBFD941E151C486A7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="rajtend_0-1731348658298.png" alt="rajtend_0-1731348658298.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Can you tell me which are not needed?&lt;/P&gt;</description>
      <pubDate>Mon, 11 Nov 2024 18:11:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1992174#M32540</guid>
      <dc:creator>rajtend</dc:creator>
      <dc:date>2024-11-11T18:11:15Z</dc:date>
    </item>
    <item>
      <title>Re: Using SDRAM for large data on imxRT1050 EVKB</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1992208#M32542</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242788"&gt;@rajtend&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I'm afraid I wouldn't be able to tell you what preprocessor definitions are not needed, since this depends on your specific application.&lt;/P&gt;
&lt;P&gt;I would recommend you compare your project with one in our SDK examples and go from there.&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Mon, 11 Nov 2024 20:40:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Using-SDRAM-for-large-data-on-imxRT1050-EVKB/m-p/1992208#M32542</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2024-11-11T20:40:20Z</dc:date>
    </item>
  </channel>
</rss>

