topic Description of the Flexspi boot clock for the nor flash wrong in i.MX RT Crossover MCUs

Description of the Flexspi boot clock for the nor flash wrong

Kalimanni — Thu, 24 Oct 2024 10:45:23 GMT

Hello,

in the reference manual rev3. from 07/2021 on page 208 it says that PFD_480_PFD1 is selected as clock source for the Flexspi at boot time for nor flash.

If i read the registers for flexspi mux and div i find the values 3 and 4. Mux value 3 means kCLOCK_Usb1PllPfd0Clk is the clock source. If i use Clock_GetFreq(kCLOCK_Usb1PllPfd0Clk) the value is 480 * 18 / 13 MHz. This divided by 5 is near 133 MHz for the nor flash. 133 MHz is also the clock value for my flash.

I can't find a possible clock mux value of PLL3 PFD1 (PFD_480_PFD1) for the Flexspi.

Is this an error in the reference manual?

Best regards,

kalimanni

回复： Description of the Flexspi boot clock for the nor flash wrong

Gavin_Jia — Tue, 05 Nov 2024 08:35:07 GMT

Hi @Kalimanni ,

Thanks for your interest in NXP MIMXRT series!

At BootROM startup, a lower frequency is used, first going at a low speed to read the Flash header, and then reconfiguring it to the user's clock frequency.

Best regards,
Gavin

回复： Description of the Flexspi boot clock for the nor flash wrong

Kalimanni — Tue, 05 Nov 2024 14:18:36 GMT

Hello Gavin_Jia,

Thanks for your answer.
Sorry, but this was not my question.
The reference manual rev3. from 07/2021 on page 208 it says that PFD_480_PFD1 is selected as clock source for the Flexspi at boot time for nor flash.
My question is:
How is it possible that at boot time PFD_480_PFD1 is selected as root clock for Flexspi?
If Flexspi can only choose between kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk and kCLOCK_SysPllPfd0Clk as root clock, how can kCLOCK_Usb1PllPfd1Clk be available at boot time?

BR
kalimanni