topic Re: SDRAM Read write issue in i.MX RT Crossover MCUs

SDRAM Read write issue

Adithya — Tue, 01 Oct 2024 11:29:19 GMT

I'm trying to read and write to SDRAM with SEMC_CM7 example code, everything is working fine with EVAL board. But if i try the same thing with our customized board which is similar to Eval board, for the same SEMC FPAGA is interfaced with addition chip select.

The SDRAM chip we used in our customized board is "W9825G6KH-52344P"

With our customized board with DATALEN of 0x1000 read and write is working fine with one change in the example code (evkbmimxrt1170_semc_cm7).

1. Disabled/commented "DCACHE_InvaliddateByRange" in our code".

2. We need to go for Read from SDRAM before going for Write operation

If we increase DATALEN to 0x2000 in example code, its failing in 32/16/8 bit Read write operation. What could be the reason, Can someone help me on this.

Pls refer attached workspace.

Re: SDRAM Read write issue

kerryzhou — Wed, 02 Oct 2024 04:59:40 GMT

Hi @Adithya ,

Thanks so much for your trust! I already don't support the RT in the community now.

Please don't worry, our other RT engineer will help you about your issues, please keep patient for the case reply.

Best Regards,

kerry

Re: SDRAM Read write issue

Sam_Gao — Tue, 08 Oct 2024 05:58:58 GMT

Hi @Adithya

It is strange becasue 'DCACHE_InvalidateByRange' is only for cache alignment.

Would you please help check with the below patch?

1. Set this marco to 0

// #define CACHE_MAINTAIN 0x01U #define CACHE_MAINTAIN 0

2. source/semc_sdram.c, add " SCB_DisableDCache()" before reading or writing.

int main(void) { /* Hardware initialize. */ BOARD_ConfigMPU(); BOARD_InitPins(); BOARD_BootClockRUN(); BOARD_InitDebugConsole(); /* Config cacheable attribute for SDRAM memory */ APP_ConfigMPU(); #if !(defined(CACHE_MAINTAIN) && CACHE_MAINTAIN) #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) { SCB_DisableDCache(); } #endif #endif PRINTF("\r\n SEMC SDRAM Example Start!\r\n"); if (BOARD_InitSEMC() != kStatus_Success) { PRINTF("\r\n SEMC SDRAM Init Failed\r\n"); } + SCB_DisableDCache(); /* 32Bit data read and write. */ SEMC_SDRAMReadWrite32Bit(); /* 16Bit data read and write. */ SEMC_SDRAMReadWrite16Bit(); /* 8Bit data read and write. */ SEMC_SDRAMReadWrite8Bit(); ... }