topic Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register in i.MX RT Crossover MCUs

IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Fri, 24 May 2019 00:17:15 GMT

According to the 1060RM setting the ERFCR will enable the Enhanced FIFO. However when I try to even read the register in the FLEXCAN example it throws a hard fault. When I tried it in my own application on a imxrt1062 I also get a hard fault at that register address. Needless to say I can't set it either.

So the question is, what is the cause of the issue and is Enhanced FIFO even enabled and the RM is incorrect?

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

TomE — Tue, 28 May 2019 01:07:49 GMT

Can you read the registers at offset zero? Can you read all the registers from 0x00 to 0x50?

... the MBs from 0x80 to 0x47f?

... the RXIMRs from 0x880 to 0x87c?

... 0xbf0 to 0xbfc?

... 0xc00 to 0xc14?

... 0xc30 to 0xd2c?

... 0x2000 - 0x204c?

... 0x3000 - 0x31fc?

Are you sure "CAN_MCR[RFEN]" isn't set?

Does the module have all of its clocks generated and enabled (Table 13-5 and CCM_CCGR7?

Tom

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

kerryzhou — Tue, 28 May 2019 10:33:27 GMT

Hi Michael Smorto,

Do you follow this procedure?

Have a great day,
Kerry

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Tue, 28 May 2019 13:37:05 GMT

Hi Kerry

Thanks for getting back to me.

For the easy answers. Yes I did follow the procedure the procedure that you reference from the manual including entering freeze mode before making the changes.

As for your question "Are you sure "CAN_MCR[RFEN]" isn't set?" - will have to do a double and check and let you know about that one as well as your other questions in your first post. In regards to the clocks being set, that I can say yes they are set for sure.

Thanks

Mike

EDIT:

In the app after setting the clocks (know this works - the sdk example works on my hardware). I do a call to:

FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true);

After that I do a call to my function:

FLEXCAN_SetRxEnhancedFifoConfig(EXAMPLE_CAN, true);

With that function looking like:

void FLEXCAN_SetRxEnhancedFifoConfig(CAN_Type *base, bool enable)
{
Serial.println("Entered FIFO Config");

//only valid for Flexcan3..........
/* Assertion. */
//assert((config) || (false == enable));

/* Enter Freeze Mode. */
FLEXCAN_EnterFreezeMode(base);
Serial.println("Entered Freeze Mode");

    if (enable)
    {
    Serial.println(CAN_ERFCR_ERFEN(1), BIN);
    delay(5000);
     Serial.println(base->ERFCR,BIN);
    delay(5000);
  base->ERFCR |= CAN_ERFCR_ERFEN(1);  //Enable enhanced FIFO <======= Dies here......
    Serial.println(base->ERFCR,BIN);
    delay(5000);
  FLEXCAN3_ERFSR = CAN_ERFSR_ERFCLR(1);  //Reset RxFIFO engine
  //Clear EFRSR bits
  FLEXCAN3_ERFSR = CAN_ERFSR_ERFUFW(0) | CAN_ERFSR_ERFOVF(0) | CAN_ERFSR_ERFWMI(0) | CAN_ERFSR_ERFDA(0);
  FLEXCAN3_ERFCR |= CAN_ERFCR_NFE(2);   //Configure total number of Rx FIFO filter elements
  FLEXCAN3_ERFCR |= CAN_ERFCR_NEXIF(3);  // number of extended ID & standard ID filter elements
  FLEXCAN3_ERFCR |= CAN_ERFSR_ERFWMI(1);  // number of messages in FIFO greater than the watermark
  FLEXCAN3_ERFIER = 0x01;      // Enable interrupts if they are to be used
  //  TBD         // Enable DMA operation in MCR[DMA]
  //FLEXCAN3_ERFCR |= CAN_ERFCR_DMALW(1);  // to configure number of words to be transfered for each data element

  //Configure filter elements by writing to the ERFFELn registers?
  //FLEXCAN3_ERFFEL0...127

    Serial.println("Registers setup");

  flexcan_fd_fifo_filter_b01_t b01;
  b01.fsch = 0b01;
  //b01.RTRfilt = 0;
  b01.std_id_flt1 = 0x000;
  //b01.RTRmsk = 0;
  b01.std_id_flt1 = 0x650;

  FLEXCAN3_ERFFEL0 = CAN_ERFFEL_FEL(&b01);
  FLEXCAN3_ERFFEL1 = CAN_ERFFEL_FEL(&b01);
}

    /* Exit Freeze Mode. */
    FLEXCAN_ExitFreezeMode(base);

FLEXCAN_EnableEnhancedFIFOInterrupts();
}

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

kerryzhou — Thu, 30 May 2019 09:07:40 GMT

Hi Michael Smorto

Before you call base->ERFCR |= CAN_ERFCR_ERFEN(1);

Please note this point:

MCR[RFEN] must be cleared so that Enhanced Rx FIFO is enabled.

I find your code didn't add the MCR[RFEN] clear code, please add it and try it again.

BTW, it's better to provide the source code, because I even can't find your definition about:flexcan_fd_fifo_filter_b01_t

Have a great day,
Kerry

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Fri, 31 May 2019 12:00:17 GMT

Hi Kerry

Sorry I didn't get back to you sooner but wrapped up in some other testing yesterday. Anyway, I cleared MCR[FREN] bit and double checked that it was cleared by outputting the register in binary. Matter of before clearing the bit I checked and it was already cleared. But anyway, I do have to advise you that I already know that I am sure there are errors in my implementation for Enhanced FIFO but figured it would debug those going forward.

Anyway here is the whole source code.

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Sun, 02 Jun 2019 11:48:44 GMT

Hi Kerry

I converted the whole app to run on the 1062EVB instead of what I sent you. Please see attached zip. Maybe easier for you to use.

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

kerryzhou — Mon, 03 Jun 2019 03:06:34 GMT

Hi Michael Smorto,

Thank you for your new code.

Do you port your code to the SDK canfd_interrupt project, now, could you tell me, what the detailed problem in your attachment, still enter the hard fault? Which code line will enter the hard fault, then I will help you to test it on my board.

Have a great day,
Kerry

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

TomE — Mon, 03 Jun 2019 04:31:17 GMT

Did you check to see what other registers in the Flexcan controller can be read? Which ones can and which ones can't may point to the problem.

> base->ERFCR |= CAN_ERFCR_ERFEN(1);

Are you sure the compiler isn't turning that into a bit or byte operation? Can you disassemble it and see what it is really doing?

The definition of the address of "ERFCR" also relies on a lot of definitions in the headers being right, and six sets of "uint8_t RESERVED_N[MMM]" being parsed properly. Can you print the address you're actually accessing to see if it is correct?

Tom

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Mon, 03 Jun 2019 11:45:07 GMT

Hi Kerry

Just reran. Yep it hard faults at enabling the enhanced FIFO. Here's a little screenshot:

I know there are other problems with my coding for Enhanced FIFO, but need to get past this first. Thanks for all your help.

Respectfully

Mike

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Mon, 03 Jun 2019 11:53:57 GMT

Hi Tom

Well right before the fault I print several registers as a sanity check of the configuration:

MCR ---- a0080f

CTRL1 ---- 15a2021

TIMER ---- cdd

IMASK1 ---- 0

IFLAG1 ---- 0

IFLAG2 ---- 0

CTRL2 ---- b30000

ESR2 ---- 6000

CRCR ---- 0

ESR2 ---- 6000

FDCTRL ---- 80008300

CLOCKS

CCM_CSCMR2 ---- 13192e0e

CCM_CCGR7 ---- fffffff3

Also, I have run the CANFD examples without a problem so know at least the normal registers are working.

As for "> base->ERFCR |= CAN_ERFCR_ERFEN(1); " I tried it this was as well "> base->ERFCR = CAN_ERFCR_ERFEN(1); " and will still get the fault.

Ok you got me on this one: "six sets of "uint8_t RESERVED_N[MMM]" being parsed properly. Can you print the address you're actually accessing to see if it is correct?" - this is what I get

ERFCR -------401d8c0c which is correct to the manual.

Can I ask you all another question - i tried adding printf in the driver itself but the compiler complained - can you tell me how to do that?

Thanks

Mike

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

TomE — Tue, 04 Jun 2019 02:30:16 GMT

> Can I ask you all another question - i tried adding printf in the driver itself but

> the compiler complained - can you tell me how to do that?

I think you edited the post because there are changes between it and the email notification I received. I'm guessing you found the "%p" option in "printf()" or cast the address to an int or something.

I don't know what operating system you're running (assuming it isn't Linux on these parts), so don't know what calls they're using for this. How to debug-print from a driver should be documented somewhere. Assuming it isn't, or you can't find it, read the other drivers until you can find some debug printing that a previous author left in there, and copy that. That driver may be including a header that is required for the functions it uses, so you'll have to check through the header sources to find which ones are needed, or just include all of them (that the other driver does) and start deleting them to find out which one or ones it needs.

Tom

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Sat, 29 Jun 2019 11:46:50 GMT

Hi All

Haven't heard anything on this issue for awhile so was wondering if there is any status or is it just not possible to do FIFO FD on the 1062.

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

michaelsmorto — Mon, 19 Aug 2019 04:26:06 GMT

Hi guys

Is there any status on this issue. Is FIFO available for FD?

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

TomE — Mon, 19 Aug 2019 07:01:57 GMT

> Is there any status on this issue.

You're too late. Because:

> Kerry Zhou @ Michael Smorto on 03/06/2019 1:06 PM

> Note:

> - We are following threads for 7 weeks after the last post, later replies are ignored
> Please open a new thread and refer to the closed one, if you have a related question at a later point in time.

So you'll have to open a new issue.

Did you manage to get debug prints working from the driver? Did you disassemble the code to make sure it is doing the right thing?

You printed some registers, but not enough. This chip has registers from 0x00 to 0x50, 0x880 to 0x97c, 0xbf0 to 0xc14, 0xc30 to 0xd2c and 0x3000 to 0x31fc. You should try to print out ALL the registers to try and find out which ones are and aren't working. It is possible there's a bug in the manual that is giving you the wrong addresses for some of those registers. This sort of mistake in these manuals is pretty common.

It is a good idea to compare the addresses with ones for the same module in other manuals. Looking for other NXP products with CAN FD support, finds the LPC546xx. And its controller is ... VERY different, because it is "MCAN" and not "FlexCAN". Dead end there... Searching finds the MPC5775, which has FlexCAN and FD. Except it has four FlexCAN modules, and two MCAN FD modules. Weird mix. The S32R27 has three FlexCAN controllers, two of which are FD. But they're different to the ones in the IMXRT1060. For a start, the last register is at offset 0xc08 from the base, and is CAN_FDCRC. That might match up with what you're seeing. It is possible the CAN controller in the IMXRT is documented in the S32R27 manual, and the chapter in the IMXRT manual might be wrong. There are also differences in that one uses addresses 0xAE0 to 0xAEC and the other one has different registers in the range 0xBF0 to 0xBFC. I'd suggest you try to print ALL the registers and see if the map matches the IMXRT or if it somehow matches the S32R27 one.

Do you have any files in the development environment that define the registers? Compare them to the manual. Do you have he program that NXP provides (MCUXpresso) that generates code and configurations for setting up the chip? See if it has register definitions inside it.

I've got an i.MX1050 here (not the FD one). I can read those addresses even though there's no peripheral there. But reading the registers of the one that is there works for the registers that are present (0x401d404c) but gives an exception for one that isn't (0x401d4050). So the access logic works OK. Are you sure you're not getting interference from the memory protection unit?

Tom

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

kerryzhou — Tue, 20 Aug 2019 02:50:48 GMT

Hi Michael Smorto ,

You don't need to create the new case, I will continue to help you in this post, it doesn't matter.

Which SDK version you are using? Do you try the newest SDK, whether you can reproduce the same problem with newest SDK for RT1060? Please update your issue project with the newest SDK, then I will find time to help you to check it, thanks a lot for your undertanding.

Kerry

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

TomE — Tue, 20 Aug 2019 04:29:27 GMT

I wrote:

> I'd suggest you try to print ALL the registers and see if the map matches the IMXRT or if it

> somehow matches the S32R27 one.

I've got an IMXRT1060 development board now.

I'm not using any SDK. I'm directly reading the module registers using GDB. Direct reads. No NXP software involvement at all. I get the same result reading the registers from "running code". If others are able to read the registers, then it is probably due to some previous register writing that some SDK component did.

The FlexCAN module in the IMXRT1060 isn't the S32R27 one.

I can read registers starting at 0x401d8000 with offsets 0x00, 0x50, 0x80, 0x100, 0x880 and 0x97c. I get a bus error on ox980. That matches the IMXRT FlexCAN module, but not the S32R27 one.

I can read 0xc08, but 0xc0c gives a bus error. This is the same as Michael Smorto is seeing.

I can't read 0xbf0, 0xc30 or 0x3000 either. None of the registers named "Enhanced" can be read.

I've tried setting MCR[FDEN] and am making sure the module is halted. RFEN is zero. Nothing I can find makes those registers readable.

The registers are behaving as if the Supervisor/User setting is wrong. That says:

Unrestricted read and write access to supervisor registers (registers identified with
S/U in Table "Module Memory Map" in Supervisor Mode or with S only) results in
access error.

A worked code example that includes setting those registers might show what other actions are required to have these registers enabled. I can't find anything in the Reference Manual saying anything about this.

Tom

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

kerryzhou — Tue, 20 Aug 2019 05:27:04 GMT

Hi Tom Evans ,

Thanks for your detail information.

If you have the official board, can you try to run the offical newest SDK project flexcan driver:

SDK_2.6.2_EVK-MIMXRT1060\boards\evkmimxrt1060\driver_examples\flexcan

Can you reproduce the problem with SDK code?

If yes, please give me modifed project which is based on the SDK, then I will double check it, and discuss it in our internal side.

Kerry

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

TomE — Tue, 20 Aug 2019 05:42:57 GMT

> If you have the official board, can you try to run the offical newest SDK project flexcan driver:

No. We're not using any of your software.

Can you put two lines of code into your SDK that tries to access these registers. Just do something like the following (using whatever the SDK uses for "printf()":

printf("FlexCAN MCR Register at 0x%08x = 0x%08x\n", 0x401d8000, *(unsigned int *)0x401d8000);
printf("FlexCAN ERFCR Register at 0x%08x = 0x%08x\n", 0x401d8c0c, *(unsigned int *)0x401d8c0c);
‍‍

I get this happening - the first one works, but the second one gives a bus fault:

[    3.300280] FlexCAN MCR Register at 0x401d8000 = 0x5980000f
[    3.302010] Thread mode exception 5, thread 0x2020b160
[    3.302020]  r0 80026084 r1 401d8c0c r2 00000000   r3 801aae7c
[    3.302030] r12 00000001 lr 80005175 ra 8001bf96 xpsr 61000000
[    3.302030] PANIC: BusFault
‍‍‍‍‍

You may need to add some sort of delay between the two statements so the first print can get out before the second one traps.

Tom

Re: IMXRT1062 Hardfault Reading CAN3 ERFCR Register

kerryzhou — Tue, 20 Aug 2019 07:15:13 GMT

Hi Tom.

If just add your code, it really has problems when read the 0x401d8c0c, it is the ERFCR register.

Please note, when the module in freeze mode, this register is written only, it means you can't read it.

From your reply, I find your 0x401d8000 = 0x5980000f.

Please check these register:

Your bit 28, and 30 is 1, it means your flexcan module is in freeze mode, that's why you read the ERFCR have hardfault.

Please disable the freeze mode, then try to read ERFCR register again.

Wish it helps you!

Kerry