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    <title>i.MX RT Crossover MCUsのトピックRe: cache issue with lwip stack</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1878054#M30672</link>
    <description>&lt;P&gt;not no USB yet , just using flexSPI for XIP boot from flash NOR and ethernet (LWIP+embedtls) for web server and ADC for ADE measurments&amp;nbsp; but no other peripherals&lt;/P&gt;</description>
    <pubDate>Thu, 30 May 2024 09:07:05 GMT</pubDate>
    <dc:creator>yosri_c</dc:creator>
    <dc:date>2024-05-30T09:07:05Z</dc:date>
    <item>
      <title>cache issue with lwip stack</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1876267#M30617</link>
      <description>&lt;P&gt;hi folks&amp;nbsp;&lt;/P&gt;&lt;P&gt;i'm currently working on integrating lwip stack in our project and we noticed that everything runs well server side&amp;nbsp; until we enable the cahce in mpu config , we looked around and found out that there's an issue with DCACHE and both rxbuffer and txbuffer shouldn't be allocated in cached region so we went ahead and set some NCACHE region in SDRAM and made sure those buffers reside well in there but no response when enabling cache&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="yosri_c_0-1716892982998.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/281154iB68F53909AB70D1B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="yosri_c_0-1716892982998.png" alt="yosri_c_0-1716892982998.png" /&gt;&lt;/span&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="yosri_c_1-1716893002691.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/281155i0B7713DA039D3B34/image-size/medium?v=v2&amp;amp;px=400" role="button" title="yosri_c_1-1716893002691.png" alt="yosri_c_1-1716893002691.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;is there anything else we're missing ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 28 May 2024 10:44:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1876267#M30617</guid>
      <dc:creator>yosri_c</dc:creator>
      <dc:date>2024-05-28T10:44:01Z</dc:date>
    </item>
    <item>
      <title>Re: cache issue with lwip stack</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1877632#M30650</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/232947"&gt;@yosri_c&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;What other peripherals are you using in your application? Do you happened to use USB as well?&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2024 21:46:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1877632#M30650</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2024-05-29T21:46:52Z</dc:date>
    </item>
    <item>
      <title>Re: cache issue with lwip stack</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1878054#M30672</link>
      <description>&lt;P&gt;not no USB yet , just using flexSPI for XIP boot from flash NOR and ethernet (LWIP+embedtls) for web server and ADC for ADE measurments&amp;nbsp; but no other peripherals&lt;/P&gt;</description>
      <pubDate>Thu, 30 May 2024 09:07:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1878054#M30672</guid>
      <dc:creator>yosri_c</dc:creator>
      <dc:date>2024-05-30T09:07:05Z</dc:date>
    </item>
    <item>
      <title>Re: cache issue with lwip stack</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1880984#M30750</link>
      <description>&lt;P&gt;Hi again&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/232947"&gt;@yosri_c&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;In this case, yes, the issue is only due to the rx and tx buffer compatibility. Please place these buffers on the NCACHE region.&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Tue, 04 Jun 2024 21:48:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/cache-issue-with-lwip-stack/m-p/1880984#M30750</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2024-06-04T21:48:24Z</dc:date>
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