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    <title>i.MX RT Crossover MCUsのトピックRT117x: FlexRAM and OCRAM</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1875541#M30600</link>
    <description>&lt;P&gt;hi,&lt;BR /&gt;we talk about memory map and specifically OCRAM.&lt;/P&gt;&lt;P&gt;On RT1175 we keep the default configuration for FlexRam, consequently (confirm or warn me if I'm wrong) 256KB ITC + 256KB DTC. Since the memory array is 2MB, and we don't use ECC, I'd like to be able to access the remaining 1.5MB of OCRAM.&lt;BR /&gt;But let's take a closer look:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mastupristi_0-1716808726238.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/280993i7E135136A301B06C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mastupristi_0-1716808726238.png" alt="mastupristi_0-1716808726238.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;The various OCRAM memories make up a contiguous array of 2MB. The FlexRAM, where does it get its 512KB total TCM, from which of these listed?&lt;/LI&gt;&lt;LI&gt;We don't use the M4 core, though, we leave all the default settings, so I have no idea whether or not CM4 is powerdown. As long as I can access those 256KB I might think about keeping the core on but maybe clock gated, or some other mode?&lt;/LI&gt;&lt;LI&gt;What happens if I try to access the OCRAM locations actually used for TCM? Is it considered an alias of the TCM memories or gives a fault, or unpredictable behavior?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;best regards&lt;/P&gt;&lt;P&gt;Max&lt;/P&gt;</description>
    <pubDate>Mon, 27 May 2024 11:21:51 GMT</pubDate>
    <dc:creator>mastupristi</dc:creator>
    <dc:date>2024-05-27T11:21:51Z</dc:date>
    <item>
      <title>RT117x: FlexRAM and OCRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1875541#M30600</link>
      <description>&lt;P&gt;hi,&lt;BR /&gt;we talk about memory map and specifically OCRAM.&lt;/P&gt;&lt;P&gt;On RT1175 we keep the default configuration for FlexRam, consequently (confirm or warn me if I'm wrong) 256KB ITC + 256KB DTC. Since the memory array is 2MB, and we don't use ECC, I'd like to be able to access the remaining 1.5MB of OCRAM.&lt;BR /&gt;But let's take a closer look:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mastupristi_0-1716808726238.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/280993i7E135136A301B06C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mastupristi_0-1716808726238.png" alt="mastupristi_0-1716808726238.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;The various OCRAM memories make up a contiguous array of 2MB. The FlexRAM, where does it get its 512KB total TCM, from which of these listed?&lt;/LI&gt;&lt;LI&gt;We don't use the M4 core, though, we leave all the default settings, so I have no idea whether or not CM4 is powerdown. As long as I can access those 256KB I might think about keeping the core on but maybe clock gated, or some other mode?&lt;/LI&gt;&lt;LI&gt;What happens if I try to access the OCRAM locations actually used for TCM? Is it considered an alias of the TCM memories or gives a fault, or unpredictable behavior?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;best regards&lt;/P&gt;&lt;P&gt;Max&lt;/P&gt;</description>
      <pubDate>Mon, 27 May 2024 11:21:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1875541#M30600</guid>
      <dc:creator>mastupristi</dc:creator>
      <dc:date>2024-05-27T11:21:51Z</dc:date>
    </item>
    <item>
      <title>Re: RT117x: FlexRAM and OCRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1876547#M30630</link>
      <description>&lt;P&gt;The mentioned OCRAM M7 is the FlexRAM, the size may vary according to the ITCM and DTCM sizes.&lt;/P&gt;
&lt;P&gt;M7 needs to be on un RUN mode, leaving it on default is okay.&lt;/P&gt;
&lt;P&gt;I don’t understand your last question, if you access an area of OCRAM M7 configured as TCM it will behave as TCM since that area was previously configured as TCM.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Memory-Map-for-i-MX-RT1170-Processor/m-p/1801550#M219626" target="_blank"&gt;Solved: Re: Memory Map for i.MX RT1170 Processor - NXP Community&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
      <pubDate>Tue, 28 May 2024 21:08:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1876547#M30630</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2024-05-28T21:08:57Z</dc:date>
    </item>
    <item>
      <title>Re: RT117x: FlexRAM and OCRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1876895#M30637</link>
      <description>&lt;BLOCKQUOTE&gt;&lt;P&gt;I don’t understand your last question, if you access an area of OCRAM M7 configured as TCM it will behave as TCM since that area was previously configured as TCM.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;As I said I keep the default configuration for TCM (256KB ITC + 256KB DTC). I was wondering what happens if I access the locations between 0x20380000 and 0x203fffff.&lt;BR /&gt;I have tried some writes and verification. It turns out that most of the attempts I only have errors in verification, but occasionally I also have a BusFault.&lt;BR /&gt;Also I wonder if writing to the locations between 0x20380000 and 0x203fffff "dirties" the TCM locations, or simply the writes do not take place.&lt;/P&gt;&lt;P&gt;best regards&lt;/P&gt;&lt;P&gt;Max&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2024 06:55:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1876895#M30637</guid>
      <dc:creator>mastupristi</dc:creator>
      <dc:date>2024-05-29T06:55:14Z</dc:date>
    </item>
    <item>
      <title>Re: RT117x: FlexRAM and OCRAM</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1881932#M30762</link>
      <description>&lt;P&gt;The result of using areas not in the flexram allocation is unpredictable and it is not suggested to do it.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jun 2024 20:36:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT117x-FlexRAM-and-OCRAM/m-p/1881932#M30762</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2024-06-05T20:36:17Z</dc:date>
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