[LPSPI] complex transfer with peripheral FIFO

MassimilianoPegaso — Thu, 04 Apr 2024 14:00:30 GMT

Hello Community,

I hope you're all doing well. I'm reaching out to seek some assistance regarding managing SPI communication with the utilization of FIFO functionalities of the peripheral.

Background: I'm currently working on a project that involves SPI communication between #i.MX-RT1050## and an ADC device. To streamline the data transfer process and enhance efficiency, I'm looking into implementing it using the peripheral command/data FIFO. However, I'm facing some challenges in integrating this feature into my project.

Request for Support: I would greatly appreciate it if anyone could provide guidance, insights, or resources on how to effectively manage SPI communication while using the peripheral command/data FIFO to manage communication with multiple CS cycles using only one call to LPSPI_MasterTransferNonBlocking or other functions.

Time Diagram Reference: I've attached an image of the time diagram illustrating the SPI communication process for reference.

Thank you in advance for your time and assistance. I look forward to your responses and insights.

Best regards.

Re: [LPSPI] complex transfer with peripheral FIFO

Kan_Li — Thu, 11 Apr 2024 07:26:00 GMT

Hi @MassimilianoPegaso ,

Multiple CS cycles mean multiple frames/transfers, I don't think one call to LPSPI_MasterTransferNonBlocking may implement such functionality, maybe you have to define a custom API based on LPSPI_MasterTransferNonBlocking.

Have a great day,
Kan

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topic [LPSPI] complex transfer with peripheral FIFO in i.MX RT Crossover MCUs

[LPSPI] complex transfer with peripheral FIFO

Re: [LPSPI] complex transfer with peripheral FIFO