LPADC DMA Configuration

akhil__ — Tue, 05 Mar 2024 20:12:31 GMT

I'm trying to configure the LPADC (Low Power Analog-to-Digital Converter) using DMA (Direct Memory Access). However, I've been unable to find any example programs for LPADC DMA configuration, making the process challenging. Could anyone provide assistance by sharing some demo programs or code snippets for configuring LPADC with DMA?

回复： LPADC DMA Configuration

Gavin_Jia — Fri, 08 Mar 2024 08:43:41 GMT

Hi @akhil__ ,

Hope you are doing well!

As you can see, there is no example project for dma+adc in the SDK. However, these threads still can inspire you, as RT MCU and Kinetis share the ADC and DMA IPs.
1. https://community.nxp.com/t5/i-MX-RT/ADC-DMA/m-p/918230
2. https://community.nxp.com/t5/Kinetis-Microcontrollers/Using-DMA-to-Emulate-ADC-Flexible-Scan-Mode-with-SDK-2-x/ta-p/1120077

They differ only in the ADC control registers. On the Kinetis, eDMA triggers the ADC to sample a different channel by continuously writing new trig values to the ADC_SC1n register. On the RT1170, eDMA can write the trig value to the SWTRIG register to achieve the same effect.
This method uses two DMA channels, one channel (channel 1) to write the data from the AD sample to RAM, and the other channel (channel 0) to write the next trig value to the SWTRIG register. the first ADC sample can be triggered by the hardware of ADC_ETC, or by the software by writing the SWTRIG directly. the ADC sampling is completed, the RESFIFO value will be written to SWTRIG. After the ADC sampling is completed, the RESFIFO value is 1, as long as the
After the ADC sampling is completed, the RESFIFO value is 1, and as long as ADC_FCTRL[FWMARK] is set to 0, the DMA request can be triggered to be sent to channel1, and after channel1 completes the data transfer, channel1 will link to channel0, which will then write the new trigger value into the SWTRIG to start the next AD sampling.

Best regards,
Gavin

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LPADC DMA Configuration

回复： LPADC DMA Configuration