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    <title>i.MX RT Crossover MCUsのトピックRe: FLEXSPI IPRXFSTS while reading</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FLEXSPI-IPRXFSTS-while-reading/m-p/1818550#M29104</link>
    <description>&lt;P&gt;Thank you for the help.&lt;/P&gt;</description>
    <pubDate>Thu, 29 Feb 2024 09:00:11 GMT</pubDate>
    <dc:creator>gavin5342</dc:creator>
    <dc:date>2024-02-29T09:00:11Z</dc:date>
    <item>
      <title>FLEXSPI IPRXFSTS while reading</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FLEXSPI-IPRXFSTS-while-reading/m-p/1816581#M29058</link>
      <description>&lt;P&gt;I have an occasional (once in ~4000 reads) failure in my application using FLEXSPI to connect to an FPGA.&amp;nbsp; The failure symptom is:&lt;/P&gt;&lt;P&gt;During a 2 byte read, IPRXFSTS[FILL] = 0 and IPRXFSTS[RDCNTR] = 1.&lt;/P&gt;&lt;P&gt;Do those status values mean that the FIFO did get filled but was subsequently read by a different task (possible as I am using FreeRTOS)?&lt;/P&gt;&lt;P&gt;Does RDCNTR keep track of all received data until the next time IPCMD[TRG] is written to kick off another transfer?&lt;/P&gt;&lt;P&gt;When a transfer is not a multiple of 8 bytes, do the final bytes increment FILL/RDCNTR anyway (that seems to be what I see) e.g.a 12 byte transfer would mean FILL=2?&lt;/P&gt;</description>
      <pubDate>Tue, 27 Feb 2024 13:31:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FLEXSPI-IPRXFSTS-while-reading/m-p/1816581#M29058</guid>
      <dc:creator>gavin5342</dc:creator>
      <dc:date>2024-02-27T13:31:03Z</dc:date>
    </item>
    <item>
      <title>Re: FLEXSPI IPRXFSTS while reading</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FLEXSPI-IPRXFSTS-while-reading/m-p/1818489#M29103</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195455"&gt;@gavin5342&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your interest in NXP MIMXRT series.&lt;/P&gt;
&lt;P&gt;1. During a 2 byte read, IPRXFSTS[FILL] = 0 and IPRXFSTS[RDCNTR] = 1.&lt;BR /&gt;Do those status values mean that the FIFO did get filled but was subsequently read by a different task (possible as I am using FreeRTOS)?&lt;BR /&gt;No, reading two bytes goes through two phases, &lt;BR /&gt;the first, when the data has been read back into RXFIFO and is awaiting further processing, IPRXFSTS[FILL] = 1 and IPRXFSTS[RDCNTR] = 0,&lt;BR /&gt;second, When data is poped once from RXFIFO, IPRXFSTS[FILL] = 0 and IPRXFSTS[RDCNTR] = 1.&lt;/P&gt;
&lt;P&gt;2. Does RDCNTR keep track of all received data until the next time IPCMD[TRG] is written to kick off another transfer?&lt;BR /&gt;Yes, RDCRDCNTR will keep track of all received data until the next time IPCMD[TRG] is written to kick off another transfer.&lt;/P&gt;
&lt;P&gt;3.When a transfer is not a multiple of 8 bytes, do the final bytes increment FILL/RDCNTR anyway (that seems to be what I see) e.g.a 12 byte transfer would mean FILL=2?&lt;BR /&gt;Yes, When the transmitted bytes are less than 16 bytes and greater than 8 bytes, the IPRXFSTS[FILL] = 2.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Hang&lt;/P&gt;</description>
      <pubDate>Thu, 29 Feb 2024 08:21:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FLEXSPI-IPRXFSTS-while-reading/m-p/1818489#M29103</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2024-02-29T08:21:27Z</dc:date>
    </item>
    <item>
      <title>Re: FLEXSPI IPRXFSTS while reading</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FLEXSPI-IPRXFSTS-while-reading/m-p/1818550#M29104</link>
      <description>&lt;P&gt;Thank you for the help.&lt;/P&gt;</description>
      <pubDate>Thu, 29 Feb 2024 09:00:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FLEXSPI-IPRXFSTS-while-reading/m-p/1818550#M29104</guid>
      <dc:creator>gavin5342</dc:creator>
      <dc:date>2024-02-29T09:00:11Z</dc:date>
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