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    <title>i.MX RT Crossover MCUsのトピックRe: imx rt: Which PLL clock?</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/imx-rt-Which-PLL-clock/m-p/1803708#M28835</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/189239"&gt;@bp1979&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;There is no such thing as a silly question, just silly people that don't ask questions. &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;PLL2 is System PLL, and PLL3 is USB1PLL.&lt;/P&gt;
&lt;P&gt;Therefore, when selecting PLL2 PFD2, you are selecting the clock output of the System PLL passed through its third Phase Fractional Divider (PFD2):&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EdwinHz_0-1707343424417.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/262404i54F613063D6EAC84/image-size/medium?v=v2&amp;amp;px=400" role="button" title="EdwinHz_0-1707343424417.png" alt="EdwinHz_0-1707343424417.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;When selecting PLL3 PFD0, you are selecting the clock output of the USB1PLL passed through its first Phase Fractional Divider (PFD0):&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EdwinHz_1-1707343618882.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/262405iD1CE7F0A5314B1D3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="EdwinHz_1-1707343618882.png" alt="EdwinHz_1-1707343618882.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;And finally, when selecting PLL3 SW, you are selecting the clock output of the USB1PLL directly:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EdwinHz_2-1707343669958.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/262406iFCBE0B91F09061CD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="EdwinHz_2-1707343669958.png" alt="EdwinHz_2-1707343669958.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;CLOCK_InitSysPfd() initializes the System PLL's PFDs, while&amp;nbsp;CLOCK_InitUsb1Pfd initializes the&amp;nbsp;USB1PLL's PFDs.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 07 Feb 2024 22:12:21 GMT</pubDate>
    <dc:creator>EdwinHz</dc:creator>
    <dc:date>2024-02-07T22:12:21Z</dc:date>
    <item>
      <title>imx rt: Which PLL clock?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/imx-rt-Which-PLL-clock/m-p/1800808#M28766</link>
      <description>&lt;P&gt;Dear NXP,&lt;/P&gt;&lt;P&gt;I might have a silly question, I hope you can still help me out. I am struggling to understand which clock sources I can set for flexspi.&lt;/P&gt;&lt;P&gt;According to the clock tool, I can choose 4 different clock sources (SEMC, PLL2 PFD2, PLL3_SW, PLL3_PDF0)&lt;/P&gt;&lt;P&gt;In fsl_clock I can set the pfdFrac of a clock. E.g. with "CLOCK_InitSysPfd"&lt;/P&gt;&lt;P&gt;But the argument to the function is only clock_pfd_t. So I can't choose PLL2 or PLL3.&lt;/P&gt;&lt;P&gt;Does that mean that "SysPfd" is either PLL2 or PLL3?&lt;/P&gt;&lt;P&gt;And if that's the case, which one is PLL3? Usb1Pfd?&lt;/P&gt;</description>
      <pubDate>Fri, 02 Feb 2024 11:21:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/imx-rt-Which-PLL-clock/m-p/1800808#M28766</guid>
      <dc:creator>bp1979</dc:creator>
      <dc:date>2024-02-02T11:21:33Z</dc:date>
    </item>
    <item>
      <title>Re: imx rt: Which PLL clock?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/imx-rt-Which-PLL-clock/m-p/1803708#M28835</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/189239"&gt;@bp1979&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;There is no such thing as a silly question, just silly people that don't ask questions. &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;PLL2 is System PLL, and PLL3 is USB1PLL.&lt;/P&gt;
&lt;P&gt;Therefore, when selecting PLL2 PFD2, you are selecting the clock output of the System PLL passed through its third Phase Fractional Divider (PFD2):&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EdwinHz_0-1707343424417.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/262404i54F613063D6EAC84/image-size/medium?v=v2&amp;amp;px=400" role="button" title="EdwinHz_0-1707343424417.png" alt="EdwinHz_0-1707343424417.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;When selecting PLL3 PFD0, you are selecting the clock output of the USB1PLL passed through its first Phase Fractional Divider (PFD0):&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EdwinHz_1-1707343618882.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/262405iD1CE7F0A5314B1D3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="EdwinHz_1-1707343618882.png" alt="EdwinHz_1-1707343618882.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;And finally, when selecting PLL3 SW, you are selecting the clock output of the USB1PLL directly:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="EdwinHz_2-1707343669958.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/262406iFCBE0B91F09061CD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="EdwinHz_2-1707343669958.png" alt="EdwinHz_2-1707343669958.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;CLOCK_InitSysPfd() initializes the System PLL's PFDs, while&amp;nbsp;CLOCK_InitUsb1Pfd initializes the&amp;nbsp;USB1PLL's PFDs.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 07 Feb 2024 22:12:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/imx-rt-Which-PLL-clock/m-p/1803708#M28835</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2024-02-07T22:12:21Z</dc:date>
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