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    <title>topic Re: IMXRT 1170  1 Lane MIPI vs 2 Lane MIPI with OV5640? in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-1170-1-Lane-MIPI-vs-2-Lane-MIPI-with-OV5640/m-p/1803416#M28825</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;We have one lane work in linux so Please check:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Using-only-one-lane-on-OV5640-MIPI-i-MX6-SabreSD/ta-p/1112353" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Using-only-one-lane-on-OV5640-MIPI-i-MX6-SabreSD/ta-p/1112353&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
    <pubDate>Wed, 07 Feb 2024 14:10:21 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2024-02-07T14:10:21Z</dc:date>
    <item>
      <title>IMXRT 1170  1 Lane MIPI vs 2 Lane MIPI with OV5640?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-1170-1-Lane-MIPI-vs-2-Lane-MIPI-with-OV5640/m-p/1800091#M28754</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I'm actually trying to get the MT9M114 which is exclusively 1 lane MIPI to work with the IMXRT1170, but using the OV5640 as a prior step to determine if using 1 lane is even possible.&lt;BR /&gt;&lt;BR /&gt;As far as I can tell, on the NXP side the only change that needs to be made is switching the define from 2 lanes to 1?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mikebaird_0-1706802942212.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/261417i719013C941FA4409/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mikebaird_0-1706802942212.png" alt="mikebaird_0-1706802942212.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I sent the command to the OV5640 to tell it to be 1 lane MIPI in the ov5640.c driver&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mikebaird_1-1706803048363.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/261418i59D1467B0FD80C98/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mikebaird_1-1706803048363.png" alt="mikebaird_1-1706803048363.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mikebaird_2-1706803096438.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/261419i350960D3BB28C240/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mikebaird_2-1706803096438.png" alt="mikebaird_2-1706803096438.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I'm debugging using LVGL onto the display.&lt;BR /&gt;I am also using the test pattern on the camera to make my life easier.&lt;BR /&gt;Here's the output I expect, and get when the camera is set to 2 lane MIPI&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mikebaird_3-1706803163138.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/261420i2C43E46FE0AD8228/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mikebaird_3-1706803163138.png" alt="mikebaird_3-1706803163138.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;However this is what I get when I setup for 1 lane MIPI:&lt;BR /&gt;(640x480 VGA,&amp;nbsp; 30 FPS)&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mikebaird_5-1706803257106.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/261422iD8C25D632BBABFB4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="mikebaird_5-1706803257106.png" alt="mikebaird_5-1706803257106.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It seems like the first 8 horizontal lines are correct. Then there's an offset?&lt;BR /&gt;As much as I like Tetris shapes, I'd like to fix this issue.&lt;BR /&gt;&lt;BR /&gt;Thanks for any suggestions / help.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Mike&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 01 Feb 2024 16:02:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-1170-1-Lane-MIPI-vs-2-Lane-MIPI-with-OV5640/m-p/1800091#M28754</guid>
      <dc:creator>mikebaird</dc:creator>
      <dc:date>2024-02-01T16:02:25Z</dc:date>
    </item>
    <item>
      <title>Re: IMXRT 1170  1 Lane MIPI vs 2 Lane MIPI with OV5640?</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-1170-1-Lane-MIPI-vs-2-Lane-MIPI-with-OV5640/m-p/1803416#M28825</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;We have one lane work in linux so Please check:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Using-only-one-lane-on-OV5640-MIPI-i-MX6-SabreSD/ta-p/1112353" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Using-only-one-lane-on-OV5640-MIPI-i-MX6-SabreSD/ta-p/1112353&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Wed, 07 Feb 2024 14:10:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-1170-1-Lane-MIPI-vs-2-Lane-MIPI-with-OV5640/m-p/1803416#M28825</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2024-02-07T14:10:21Z</dc:date>
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