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    <title>topic Re: EDMA interrupts solution in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/EDMA-interrupts/m-p/1774679#M28014</link>
    <description>&lt;P&gt;&lt;FONT size="2"&gt;Thank you EdwinHz,&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;I'm trying to have a more direct approach to the MPU registers...I'm primarily a "hardware man" &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt; and I need to develop firmware too, but I'm not that good...&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;For example I would need to better understand how the handles work (any help ?)...I'm trying to avoid them now.&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;This is my solution, but I don't know if it is right:&lt;/FONT&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt;&lt;SPAN&gt; IRQ_DMA_CH0 0&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt;&lt;SPAN&gt; IRQ_DMA_CH1 1&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;(*&lt;/SPAN&gt;&lt;SPAN&gt;volatile&lt;/SPAN&gt;&lt;SPAN&gt; _VectorsRam[80+16])(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;);&amp;nbsp; //Table 4-2. CM7 domain interrupt summary, IMXRT1010-reference.pdf p.38&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;inline&lt;/SPAN&gt; &lt;SPAN&gt;void&lt;/SPAN&gt; &lt;SPAN&gt;attachInterruptVector&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;uint16_t&lt;/SPAN&gt;&lt;SPAN&gt; irq, &lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; (*function)(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;)) &lt;/SPAN&gt;&lt;SPAN&gt;__attribute__&lt;/SPAN&gt;&lt;SPAN&gt;((always_inline, unused));&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;inline&lt;/SPAN&gt; &lt;SPAN&gt;void&lt;/SPAN&gt; &lt;SPAN&gt;attachInterruptVector&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;uint16_t&lt;/SPAN&gt;&lt;SPAN&gt; irq, &lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; (*function)(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;)) { _VectorsRam[irq + 16] = function; &lt;/SPAN&gt;&lt;SPAN&gt;asm&lt;/SPAN&gt; &lt;SPAN&gt;volatile&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;""&lt;/SPAN&gt;&lt;SPAN&gt;: : :&lt;/SPAN&gt;&lt;SPAN&gt;"memory"&lt;/SPAN&gt;&lt;SPAN&gt;); }&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;//An interrupt routine can be run when the DMA channel completes the entire transfer, and also optionally when half of the transfer is completed&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;void&lt;/SPAN&gt; &lt;SPAN&gt;DMAattachInterrupt&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; (*isr)(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;), &lt;/SPAN&gt;&lt;SPAN&gt;uint16_t&lt;/SPAN&gt;&lt;SPAN&gt; channel) {&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;_VectorsRam[channel+IRQ_DMA_CH0+16]=isr;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;NVIC_ENABLE_IRQ(IRQ_DMA_CH0+0);&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;main(){&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;...&lt;/P&gt;&lt;P&gt;...&lt;/P&gt;&lt;P&gt;...&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;DMAattachInterrupt(INT_0_IRQHANDLER, 0); &lt;/SPAN&gt;&lt;SPAN&gt;//Attach interrupt channel 1&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;DMAattachInterrupt(INT_1_IRQHANDLER, ); //Attach interrupt channel 1&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;Luigi&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Thu, 14 Dec 2023 09:43:13 GMT</pubDate>
    <dc:creator>LuigiV</dc:creator>
    <dc:date>2023-12-14T09:43:13Z</dc:date>
    <item>
      <title>EDMA interrupts</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/EDMA-interrupts/m-p/1773268#M27969</link>
      <description>&lt;P&gt;I need your help again...&lt;/P&gt;&lt;P&gt;I'm developing a new project, I have to interface an external codec (but first I'll use the WM8960) and I need to transmit and receive blocks of 128 word(32 bits) in a continuous mode to and from the CODEC.&lt;/P&gt;&lt;P&gt;I use the DMA channel 1 to receive and the DMA channel 0 to transmit; I configured the TCD registers but I don't know how to link the interrupt routines to the DMA; this is the DMA setting:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;edma_tcd_t&lt;/SPAN&gt;&lt;SPAN&gt; DMAmystruct;&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;edma_tcd_t&lt;/SPAN&gt;&lt;SPAN&gt; *mytcd;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;mytcd=&amp;amp;DMAmystruct;&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;//DMA0_IRQn interrupt handler transmit&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; INT_0_IRQHANDLER(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;){&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_ClearChannelStatusFlags((&lt;/SPAN&gt;&lt;SPAN&gt;DMA_Type&lt;/SPAN&gt;&lt;SPAN&gt; *)0x400E8000, 0, &lt;/SPAN&gt;&lt;SPAN&gt;kEDMA_InterruptFlag&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;//DMA0_IRQn interrupt handler receive&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; INT_1_IRQHANDLER(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;){&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_ClearChannelStatusFlags((&lt;/SPAN&gt;&lt;SPAN&gt;DMA_Type&lt;/SPAN&gt;&lt;SPAN&gt; *)0x400E8000, 1, &lt;/SPAN&gt;&lt;SPAN&gt;kEDMA_InterruptFlag&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;SPAN&gt;//DMA channel 1, receive&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;SADDR&lt;/SPAN&gt;&lt;SPAN&gt;=(__IO &lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)((&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)I2S1_RDR0);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;SOFF&lt;/SPAN&gt;&lt;SPAN&gt;=0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;ATTR&lt;/SPAN&gt;&lt;SPAN&gt;=0x22;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;NBYTES&lt;/SPAN&gt;&lt;SPAN&gt;=4;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;SLAST&lt;/SPAN&gt;&lt;SPAN&gt;=0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;DADDR&lt;/SPAN&gt;&lt;SPAN&gt;=(__IO &lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)i2s2_rx_buffer;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;DOFF&lt;/SPAN&gt;&lt;SPAN&gt;=4;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;CITER&lt;/SPAN&gt;&lt;SPAN&gt;=256;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;DLAST_SGA&lt;/SPAN&gt;&lt;SPAN&gt;=-1024;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;BITER&lt;/SPAN&gt;&lt;SPAN&gt;=256;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;CSR&lt;/SPAN&gt;&lt;SPAN&gt;=0x02; &lt;/SPAN&gt;&lt;SPAN&gt;//Interrupt on major loop completion&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_InstallTCD(mydmabase,1,mytcd); &lt;/SPAN&gt;&lt;SPAN&gt;//Install I2S receive DMA channel 1&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;//DMA channel 0, transmit&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;SADDR&lt;/SPAN&gt;&lt;SPAN&gt;=(__IO &lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)i2s2_rx_buffer;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;SOFF&lt;/SPAN&gt;&lt;SPAN&gt;=4;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;ATTR&lt;/SPAN&gt;&lt;SPAN&gt;=0x22;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;NBYTES&lt;/SPAN&gt;&lt;SPAN&gt;=4;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;SLAST&lt;/SPAN&gt;&lt;SPAN&gt;=-1024;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;DADDR&lt;/SPAN&gt;&lt;SPAN&gt;=(__IO &lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)((&lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt;&lt;SPAN&gt;)I2S1_TDR0);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;DOFF&lt;/SPAN&gt;&lt;SPAN&gt;=0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;CITER&lt;/SPAN&gt;&lt;SPAN&gt;=256;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;DLAST_SGA&lt;/SPAN&gt;&lt;SPAN&gt;=0;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;BITER&lt;/SPAN&gt;&lt;SPAN&gt;=256;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DMAmystruct.&lt;/SPAN&gt;&lt;SPAN&gt;CSR&lt;/SPAN&gt;&lt;SPAN&gt;=0x02; &lt;/SPAN&gt;&lt;SPAN&gt;//Interrupt on major loop completion&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;EDMA_InstallTCD(mydmabase,0,mytcd); &lt;/SPAN&gt;&lt;SPAN&gt;//Install I2S transmit DMA channel 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks, Luigi&lt;/SPAN&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 12 Dec 2023 16:41:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/EDMA-interrupts/m-p/1773268#M27969</guid>
      <dc:creator>LuigiV</dc:creator>
      <dc:date>2023-12-12T16:41:03Z</dc:date>
    </item>
    <item>
      <title>Re: EDMA interrupts</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/EDMA-interrupts/m-p/1774201#M27996</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/225874"&gt;@LuigiV&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;Have you looked into the provided example codes from the SDK? You could link by using software based transfer requests, which can be achieved by setting&amp;nbsp;TCDn_CSR[START], as described on section "6.6.1 eDMA initialization". This is also done by the "void EDMA_StartTransfer(edma_handle_t *handle)" routine from the eDMA driver API.&lt;/P&gt;&lt;P&gt;Let me know if this helps.&lt;/P&gt;&lt;P&gt;BR,&lt;BR /&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Wed, 13 Dec 2023 21:54:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/EDMA-interrupts/m-p/1774201#M27996</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2023-12-13T21:54:04Z</dc:date>
    </item>
    <item>
      <title>Re: EDMA interrupts solution</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/EDMA-interrupts/m-p/1774679#M28014</link>
      <description>&lt;P&gt;&lt;FONT size="2"&gt;Thank you EdwinHz,&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;I'm trying to have a more direct approach to the MPU registers...I'm primarily a "hardware man" &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt; and I need to develop firmware too, but I'm not that good...&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;For example I would need to better understand how the handles work (any help ?)...I'm trying to avoid them now.&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;This is my solution, but I don't know if it is right:&lt;/FONT&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt;&lt;SPAN&gt; IRQ_DMA_CH0 0&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt;&lt;SPAN&gt; IRQ_DMA_CH1 1&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;(*&lt;/SPAN&gt;&lt;SPAN&gt;volatile&lt;/SPAN&gt;&lt;SPAN&gt; _VectorsRam[80+16])(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;);&amp;nbsp; //Table 4-2. CM7 domain interrupt summary, IMXRT1010-reference.pdf p.38&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;inline&lt;/SPAN&gt; &lt;SPAN&gt;void&lt;/SPAN&gt; &lt;SPAN&gt;attachInterruptVector&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;uint16_t&lt;/SPAN&gt;&lt;SPAN&gt; irq, &lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; (*function)(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;)) &lt;/SPAN&gt;&lt;SPAN&gt;__attribute__&lt;/SPAN&gt;&lt;SPAN&gt;((always_inline, unused));&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;inline&lt;/SPAN&gt; &lt;SPAN&gt;void&lt;/SPAN&gt; &lt;SPAN&gt;attachInterruptVector&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;uint16_t&lt;/SPAN&gt;&lt;SPAN&gt; irq, &lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; (*function)(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;)) { _VectorsRam[irq + 16] = function; &lt;/SPAN&gt;&lt;SPAN&gt;asm&lt;/SPAN&gt; &lt;SPAN&gt;volatile&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;""&lt;/SPAN&gt;&lt;SPAN&gt;: : :&lt;/SPAN&gt;&lt;SPAN&gt;"memory"&lt;/SPAN&gt;&lt;SPAN&gt;); }&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;//An interrupt routine can be run when the DMA channel completes the entire transfer, and also optionally when half of the transfer is completed&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;void&lt;/SPAN&gt; &lt;SPAN&gt;DMAattachInterrupt&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt; (*isr)(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;), &lt;/SPAN&gt;&lt;SPAN&gt;uint16_t&lt;/SPAN&gt;&lt;SPAN&gt; channel) {&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;_VectorsRam[channel+IRQ_DMA_CH0+16]=isr;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;NVIC_ENABLE_IRQ(IRQ_DMA_CH0+0);&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;main(){&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;...&lt;/P&gt;&lt;P&gt;...&lt;/P&gt;&lt;P&gt;...&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;DMAattachInterrupt(INT_0_IRQHANDLER, 0); &lt;/SPAN&gt;&lt;SPAN&gt;//Attach interrupt channel 1&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;&lt;SPAN&gt;DMAattachInterrupt(INT_1_IRQHANDLER, ); //Attach interrupt channel 1&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="2"&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;Luigi&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 14 Dec 2023 09:43:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/EDMA-interrupts/m-p/1774679#M28014</guid>
      <dc:creator>LuigiV</dc:creator>
      <dc:date>2023-12-14T09:43:13Z</dc:date>
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