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    <title>topic Re: LPSPI with GPIO as Chip Select and Changing CPOL / CPHA (i.MXRT1050/1160) in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-with-GPIO-as-Chip-Select-and-Changing-CPOL-CPHA-i-MXRT1050/m-p/1757112#M27565</link>
    <description>&lt;P class="lia-align-justify"&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/170033"&gt;@christian_mauderer&lt;/a&gt;,&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;Unfortunately, there is not possible to manually set the idle level of the SPI clock line between transfers &lt;SPAN&gt;without doing a whole byte of dummy transfer&lt;/SPAN&gt;. As mentioned in the &lt;A href="https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1050-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1050" target="_self"&gt;i.MX RT1050 Processor Reference Manual&lt;/A&gt;, the CPOL bit cannot be modified during a data transfer:&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="RaRo_0-1699988209705.png" style="width: 432px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/249793iE2C572FC1F349D85/image-dimensions/432x155?v=v2" width="432" height="155" role="button" title="RaRo_0-1699988209705.png" alt="RaRo_0-1699988209705.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;[Table 47-3. LPSPI Command Word in Master mode]&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;Kind regards, Raul.&lt;/P&gt;</description>
    <pubDate>Tue, 14 Nov 2023 18:57:59 GMT</pubDate>
    <dc:creator>RaRo</dc:creator>
    <dc:date>2023-11-14T18:57:59Z</dc:date>
    <item>
      <title>LPSPI with GPIO as Chip Select and Changing CPOL / CPHA (i.MXRT1050/1160)</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-with-GPIO-as-Chip-Select-and-Changing-CPOL-CPHA-i-MXRT1050/m-p/1756234#M27549</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I'm working with an application that runs on a i.MXRT1050 and 1160 with a custom LPSPI driver. I use GPIOs for the chip select pins.&lt;/P&gt;&lt;P&gt;Unluckily, I have two SPI devices connected, that use different CPOL settings. So I have to switch these settings between the transfers. With GPIOs as chip select, I first set the GPIO and then start the transfer via TCR / TDR. Due to that, the idle level of the clock line changes &lt;EM&gt;after&lt;/EM&gt; the chip is selected and the device chip interprets that as a clock.&lt;/P&gt;&lt;P&gt;Is there a possibility to manually set the idle level of the SPI clock line between two SPI transfers without doing a whole byte of dummy transfer?&lt;/P&gt;&lt;P&gt;With kind regards&lt;/P&gt;&lt;P&gt;Christian&lt;/P&gt;</description>
      <pubDate>Mon, 13 Nov 2023 11:14:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-with-GPIO-as-Chip-Select-and-Changing-CPOL-CPHA-i-MXRT1050/m-p/1756234#M27549</guid>
      <dc:creator>christian_mauderer</dc:creator>
      <dc:date>2023-11-13T11:14:52Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI with GPIO as Chip Select and Changing CPOL / CPHA (i.MXRT1050/1160)</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-with-GPIO-as-Chip-Select-and-Changing-CPOL-CPHA-i-MXRT1050/m-p/1757112#M27565</link>
      <description>&lt;P class="lia-align-justify"&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/170033"&gt;@christian_mauderer&lt;/a&gt;,&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;Unfortunately, there is not possible to manually set the idle level of the SPI clock line between transfers &lt;SPAN&gt;without doing a whole byte of dummy transfer&lt;/SPAN&gt;. As mentioned in the &lt;A href="https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1050-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1050" target="_self"&gt;i.MX RT1050 Processor Reference Manual&lt;/A&gt;, the CPOL bit cannot be modified during a data transfer:&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="RaRo_0-1699988209705.png" style="width: 432px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/249793iE2C572FC1F349D85/image-dimensions/432x155?v=v2" width="432" height="155" role="button" title="RaRo_0-1699988209705.png" alt="RaRo_0-1699988209705.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;[Table 47-3. LPSPI Command Word in Master mode]&lt;/P&gt;
&lt;P class="lia-align-justify"&gt;Kind regards, Raul.&lt;/P&gt;</description>
      <pubDate>Tue, 14 Nov 2023 18:57:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-with-GPIO-as-Chip-Select-and-Changing-CPOL-CPHA-i-MXRT1050/m-p/1757112#M27565</guid>
      <dc:creator>RaRo</dc:creator>
      <dc:date>2023-11-14T18:57:59Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI with GPIO as Chip Select and Changing CPOL / CPHA (i.MXRT1050/1160)</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-with-GPIO-as-Chip-Select-and-Changing-CPOL-CPHA-i-MXRT1050/m-p/1757387#M27577</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206649"&gt;@RaRo&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;thanks for your response. It's what I assumed. I'll find a way to work with it.&lt;/P&gt;&lt;P&gt;With best regards&lt;/P&gt;&lt;P&gt;Christian Mauderer&lt;/P&gt;</description>
      <pubDate>Wed, 15 Nov 2023 07:34:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/LPSPI-with-GPIO-as-Chip-Select-and-Changing-CPOL-CPHA-i-MXRT1050/m-p/1757387#M27577</guid>
      <dc:creator>christian_mauderer</dc:creator>
      <dc:date>2023-11-15T07:34:18Z</dc:date>
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