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    <title>i.MX RT Crossover MCUsのトピックRe: i.MX RT CRC calculations</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-CRC-calculations/m-p/747199#M275</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, as you can see in the datasheet:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;Security functions are enabled and accelerated by the following hardware:&lt;/P&gt;&lt;P&gt;• High Assurance Boot (HAB)&lt;/P&gt;&lt;P&gt;• Data Co-Processor (DCP):&lt;/P&gt;&lt;P&gt;— AES-128, ECB, and CBC mode&lt;/P&gt;&lt;P&gt;— SHA-1 and SHA-256&lt;/P&gt;&lt;P&gt;— CRC-32&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 26 Dec 2017 09:01:40 GMT</pubDate>
    <dc:creator>Rita_Wang</dc:creator>
    <dc:date>2017-12-26T09:01:40Z</dc:date>
    <item>
      <title>i.MX RT CRC calculations</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-CRC-calculations/m-p/747198#M274</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The datasheet for i.MX RT1050 states that there is hardware support for CRC-32 calculations, but when looking in the reference manual CRC-32 is not mentioned. Does the processor provide an interface for hardware accelerated CRC-32 calculations for custom usage?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Tajs&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Datasheet page 4:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;Security functions are enabled and accelerated by the following hardware:&lt;/P&gt;&lt;P&gt;• High Assurance Boot (HAB)&lt;/P&gt;&lt;P&gt;• Data Co-Processor (DCP):&lt;/P&gt;&lt;P&gt;— AES-128, ECB, and CBC mode&lt;/P&gt;&lt;P&gt;— SHA-1 and SHA-256&lt;/P&gt;&lt;P&gt;— CRC-32&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Reference manual page 446:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;For security purposes, the Data Co-Processor (DCP) provides hardware acceleration for&lt;/P&gt;&lt;P&gt;the cryptographic algorithms. The features of DCP are:&lt;/P&gt;&lt;P&gt;• Encryption Algorithms: AES-128 (ECB and CBC modes)&lt;/P&gt;&lt;P&gt;• Hashing Algorithms: SHA-1 and SHA-256&lt;/P&gt;&lt;P&gt;• Key selection from the SNVS, DCP internal key storage, or general memory&lt;/P&gt;&lt;P&gt;• Internal Memory for storing up to four AES-128 keys—when a key is written to a&lt;/P&gt;&lt;P&gt;key slot it can be read only by the DCP AES-128 engine&lt;/P&gt;&lt;P&gt;• IP slave interface&lt;/P&gt;&lt;P&gt;• DMA&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Nov 2017 07:52:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-CRC-calculations/m-p/747198#M274</guid>
      <dc:creator>tajsbrandt</dc:creator>
      <dc:date>2017-11-03T07:52:15Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX RT CRC calculations</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-CRC-calculations/m-p/747199#M275</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, as you can see in the datasheet:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;Security functions are enabled and accelerated by the following hardware:&lt;/P&gt;&lt;P&gt;• High Assurance Boot (HAB)&lt;/P&gt;&lt;P&gt;• Data Co-Processor (DCP):&lt;/P&gt;&lt;P&gt;— AES-128, ECB, and CBC mode&lt;/P&gt;&lt;P&gt;— SHA-1 and SHA-256&lt;/P&gt;&lt;P&gt;— CRC-32&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Dec 2017 09:01:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-CRC-calculations/m-p/747199#M275</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2017-12-26T09:01:40Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX RT CRC calculations</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-CRC-calculations/m-p/1270381#M14033</link>
      <description>&lt;P&gt;I agree with the OP.&amp;nbsp; I can see that there is hardware in the Data co-processor to perform a CRC-32 but I can't see anywhere how I could do this.&lt;/P&gt;&lt;P&gt;To be clear, my requirements are that I have a couple of hundred bytes in internal RAM and I want to calculate the CRC-32 of them.&amp;nbsp; Can anyone tell me which registers I need to set up to get the co-processor to perform that calculation for me?&lt;/P&gt;</description>
      <pubDate>Thu, 29 Apr 2021 14:42:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-CRC-calculations/m-p/1270381#M14033</guid>
      <dc:creator>antonypace</dc:creator>
      <dc:date>2021-04-29T14:42:08Z</dc:date>
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