i.MX RT Crossover MCUsのトピック回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

SRAM IO refresh failed due to error in RT1175 CM7 core program

liuhailong — Mon, 30 Oct 2023 01:53:24 GMT

SRAMIO refresh failed due to error in RT1170 CM7 core program，Using SEMC's SDRAM official example program, add their own modified code, make it into SRAM program, SRAMIO refresh in the RT1170 CM7 core program error, run failure.The same program in cm4 core can run normally, want to ask, CM7 core should be configured?Procedural Reference Annex.

#i.MX RT

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

liuhailong — Mon, 30 Oct 2023 07:03:17 GMT

@Pavel_Hernandez

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

jingpan — Wed, 01 Nov 2023 02:36:05 GMT

Hi @liuhailong ,

Here is SEMC configuration for SRAM 8bit. If you want to use 16bit sram, just set portsize to 16. You should adjust other timing parameters according to your sram.

status_t BOARD_InitSEMC(void) { semc_config_t config; semc_sdram_config_t sdramconfig; semc_sram_config_t sramconfig; semc_nor_config_t norconfig; uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ; /* Initializes the MAC configure structure to zero. */ memset(&config, 0, sizeof(semc_config_t)); memset(&sdramconfig, 0, sizeof(semc_sdram_config_t)); /* Initialize SEMC. */ SEMC_GetDefaultConfig(&config); config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */ SEMC_Init(SEMC, &config); /* Configure SRAM */ sramconfig.cePinMux = kSEMC_MUXRDY; sramconfig.address = EXAMPLE_SRAM_START_ADDRESS; sramconfig.memsize_kbytes = 256 * 1024; sramconfig.addrPortWidth = 24; sramconfig.advActivePolarity = kSEMC_AdvActiveLow; sramconfig.addrMode = kSEMC_AddrDataNonMux; sramconfig.burstLen = kSEMC_Nor_BurstLen4; sramconfig.portSize = kSEMC_PortSize8Bit; sramconfig.syncMode = kSEMC_AsyncMode; sramconfig.waitEnable = false; sramconfig.advLevelCtrl = kSEMC_AdvLow; sramconfig.tCeSetup_Ns = 20; sramconfig.tCeHold_Ns = 20; sramconfig.tCeInterval_Ns = 100; sramconfig.readHoldTime_Ns = 20; sramconfig.tAddrSetup_Ns = 20; sramconfig.tAddrHold_Ns = 20; sramconfig.tWeLow_Ns = 20; sramconfig.tWeHigh_Ns = 20; sramconfig.tReLow_Ns = 20; sramconfig.tReHigh_Ns = 20; sramconfig.tTurnAround_Ns = 20; sramconfig.tAddr2WriteHold_Ns = 20; sramconfig.tWriteSetup_Ns = 20; sramconfig.tWriteHold_Ns = 20; sramconfig.latencyCount = 2; sramconfig.readCycle = 2; sramconfig.delayChain = 2; sramconfig.waitSample = 1; sramconfig.addr27 = kSEMC_MORA27_NONE; if (SEMC_ConfigureSRAM(EXAMPLE_SEMC, &sramconfig, clockFrq) != kStatus_Success) { PRINTF("SEMC SRAM configuration is failed\r\n"); } EXAMPLE_SEMC->IOCR = (EXAMPLE_SEMC->IOCR & ~(SEMC_IOCR_MUX_CLKX0_MASK | SEMC_IOCR_MUX_CLKX1_MASK)) | SEMC_IOCR_MUX_CLKX0(2) | SEMC_IOCR_MUX_CLKX1(2) | SEMC_IOCR_CLKX0_AO_MASK; EXAMPLE_SEMC->IOCR = (EXAMPLE_SEMC->IOCR & ~SEMC_IOCR_MUX_RDY_MASK) | SEMC_IOCR_MUX_RDY(6); }

Regards,

Jing

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

liuhailong — Wed, 01 Nov 2023 03:00:55 GMT

hello thanks

According to your description, there are two questions you would like to ask.

EXAMPLE_SEMC->IOCR = (EXAMPLE_SEMC->IOCR & ~(SEMC_IOCR_MUX_CLKX0_MASK | SEMC_IOCR_MUX_CLKX1_MASK)) |
                SEMC_IOCR_MUX_CLKX0(2) | SEMC_IOCR_MUX_CLKX1(2) | SEMC_IOCR_CLKX0_AO_MASK;
    EXAMPLE_SEMC->IOCR = (EXAMPLE_SEMC->IOCR & ~SEMC_IOCR_MUX_RDY_MASK) | SEMC_IOCR_MUX_RDY(6);

What parameters are configured?

   sramconfig.cePinMux = kSEMC_MUXRDY;
    sramconfig.address = EXAMPLE_SRAM_START_ADDRESS;

Haven't the following two lines of code been configured?

2.Do you give CM7 kernel parameters configuration for the program I write?My same code failed in CM4 core, could you tell me what's the difference between MRT1175 CM7 and CM4 core for SRAM? @jingpan

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

jingpan — Wed, 01 Nov 2023 09:40:57 GMT

Hi @liuhailong ,

I use SEMC_RDY pin as CE#. Start address is 0x90000000. But you can set to any address from 0x80000000 to 0xe0000000.

There is no difference to CM7 and CM4. You can use cm7 to config SEMC. The result is same.

Regards,

Jing

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

liuhailong — Thu, 02 Nov 2023 00:55:56 GMT

SRAM can only use 0XC0000000, and is the SEMC region, I want to ask, the SEMC3 address in the figure is 0xC0000000, why I write the code, in CM7 can not achieve the results, and CM4 can, can refer to my latest attachments

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

jingpan — Thu, 02 Nov 2023 09:02:22 GMT

Hi @liuhailong ,

Please modify two place.

And in board.c

Regards,

Jing

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

liuhailong — Fri, 03 Nov 2023 00:44:25 GMT

hello，thanksThe first picture shows the configuration of sdram. Please ask if there is a configuration of sdram. The second picture is region 1, but I need to use region 3, SRAM's exclusive region.

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

jingpan — Fri, 03 Nov 2023 07:20:55 GMT

Hi,

1. It's just a name. You can rename it to SRAM or any thing else. Please focus on address.

2. SEMC0~SEMCn belong to SEMC address range.

Regards,

Jing

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

liuhailong — Fri, 03 Nov 2023 08:09:20 GMT

Ok my problem solved，can you tell me the reasons that cm4 program does not need to be set，But CM7 has to board.c and settings like that you give me the two pictures?

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

jingpan — Tue, 07 Nov 2023 03:21:57 GMT

Hi @liuhailong ,

Their MPU and control code is different.

Regards,

Jing

回复： SRAM IO refresh failed due to error in RT1175 CM7 core program

liuhailong — Tue, 07 Nov 2023 05:13:06 GMT

thanks a lot