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    <title>topic Re: SRAM CS definition in i.MXRT1170 in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1749856#M27374</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/169053"&gt;@Omar_Anguiano&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your kindly answer.&lt;/P&gt;&lt;P&gt;CS&lt;STRONG&gt;n&lt;/STRONG&gt; is used in SRAM device &lt;STRONG&gt;n&lt;/STRONG&gt;, and its ChipEnable signal is CE# &lt;STRONG&gt;n&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;n = 0 to 3.&lt;/P&gt;&lt;P&gt;Is my understanding correct?&lt;/P&gt;</description>
    <pubDate>Wed, 01 Nov 2023 00:50:47 GMT</pubDate>
    <dc:creator>Eugene3</dc:creator>
    <dc:date>2023-11-01T00:50:47Z</dc:date>
    <item>
      <title>SRAM CS definition in i.MXRT1170</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1745654#M27317</link>
      <description>&lt;P&gt;There are some wordings about SRAM chip select in the i.MXRT1170 reference manual.&lt;/P&gt;&lt;P&gt;"SRAM CE# X" is used on&amp;nbsp;IOCR section.&lt;/P&gt;&lt;P&gt;"SRAM CS X" is used on&amp;nbsp;BRn section.&lt;/P&gt;&lt;P&gt;"SRAM device X" is used on SRAMCRn section.&lt;/P&gt;&lt;P&gt;Are "SRAM CE# 0", "SRAM CS 0" and "SRAM device 0" same meaning?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 25 Oct 2023 06:18:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1745654#M27317</guid>
      <dc:creator>Eugene3</dc:creator>
      <dc:date>2023-10-25T06:18:35Z</dc:date>
    </item>
    <item>
      <title>Re: SRAM CS definition in i.MXRT1170</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1749850#M27373</link>
      <description>&lt;P&gt;SRAM CE# is used as there are some pins that can optionally be configurable as Chip Enable.&lt;BR /&gt;In BRn CS is referred to as SRAM devices that can be connected to SEMC, as you know you can connect up to 4 devices with 4 different CS.&lt;BR /&gt;SRAM CSn can be used to refer to a specific device e.g. CS0 is used in SRAM device 0; while CE# refers specifically to the ChipEnable signal.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
      <pubDate>Wed, 01 Nov 2023 00:33:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1749850#M27373</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2023-11-01T00:33:42Z</dc:date>
    </item>
    <item>
      <title>Re: SRAM CS definition in i.MXRT1170</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1749856#M27374</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/169053"&gt;@Omar_Anguiano&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your kindly answer.&lt;/P&gt;&lt;P&gt;CS&lt;STRONG&gt;n&lt;/STRONG&gt; is used in SRAM device &lt;STRONG&gt;n&lt;/STRONG&gt;, and its ChipEnable signal is CE# &lt;STRONG&gt;n&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;n = 0 to 3.&lt;/P&gt;&lt;P&gt;Is my understanding correct?&lt;/P&gt;</description>
      <pubDate>Wed, 01 Nov 2023 00:50:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1749856#M27374</guid>
      <dc:creator>Eugene3</dc:creator>
      <dc:date>2023-11-01T00:50:47Z</dc:date>
    </item>
    <item>
      <title>Re: SRAM CS definition in i.MXRT1170</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1750502#M27397</link>
      <description>&lt;P&gt;Your understanding is correct.&lt;BR /&gt;It is important to clarify that CE and CS make reference to the same signal.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
      <pubDate>Wed, 01 Nov 2023 20:03:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1750502#M27397</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2023-11-01T20:03:12Z</dc:date>
    </item>
    <item>
      <title>Re: SRAM CS definition in i.MXRT1170</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1750597#M27398</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/169053"&gt;@Omar_Anguiano&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you. I completely understand.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 01 Nov 2023 23:41:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SRAM-CS-definition-in-i-MXRT1170/m-p/1750597#M27398</guid>
      <dc:creator>Eugene3</dc:creator>
      <dc:date>2023-11-01T23:41:09Z</dc:date>
    </item>
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