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    <title>i.MX RT Crossover MCUs中的主题 Re: iMX RT1170 Shared Memory</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1748956#M27360</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/223203"&gt;@BTasdemir&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I'll look for any documents that can help you.&lt;/P&gt;
&lt;P&gt;Meanwhile, I found this posts that could help you.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-RT/How-to-modify-the-default-ITCM-DTCM-OCRAM-memory-allocations-for/td-p/1050499" target="_self"&gt;How to modify the default ITCM/DTCM/OCRAM memory allocations for i.MX RT1064&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Cortex-M4-bare-metal-application-cannot-read-data-from-the/m-p/1337227" target="_self"&gt;Cortex-M4 bare-metal application cannot read data from the shared memory(OCRAM)&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/td-p/911056" target="_self"&gt;What is OCRAM?&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Read-access-to-OCRAM-from-M4-core/m-p/1333836" target="_self"&gt;Read access to OCRAM from M4 core&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Some of these threads are from i.MX processor posts, however they can provide usefull information.&lt;/P&gt;
&lt;P&gt;I'll let you know if we have better documentation regarding your question. I'll look into it.&lt;/P&gt;
&lt;P&gt;Best Regards, Miguel.&lt;/P&gt;</description>
    <pubDate>Mon, 30 Oct 2023 20:29:06 GMT</pubDate>
    <dc:creator>Miguel04</dc:creator>
    <dc:date>2023-10-30T20:29:06Z</dc:date>
    <item>
      <title>iMX RT1170 Shared Memory</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1748527#M27356</link>
      <description>&lt;P&gt;Hi NXP Engineers,&lt;/P&gt;&lt;P&gt;We have been working with iMX RT1170. I reviewed the document called AN13264. I made the communication between the two cores with the MU peripheral but I have to use shared memory. For example, I want to use OCRAM between 0x2000000 and 0x2200000 as shared. Do you have a detailed document and sample project regarding this?&lt;/P&gt;</description>
      <pubDate>Mon, 30 Oct 2023 08:34:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1748527#M27356</guid>
      <dc:creator>BTasdemir</dc:creator>
      <dc:date>2023-10-30T08:34:53Z</dc:date>
    </item>
    <item>
      <title>Re: iMX RT1170 Shared Memory</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1748956#M27360</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/223203"&gt;@BTasdemir&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I'll look for any documents that can help you.&lt;/P&gt;
&lt;P&gt;Meanwhile, I found this posts that could help you.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-RT/How-to-modify-the-default-ITCM-DTCM-OCRAM-memory-allocations-for/td-p/1050499" target="_self"&gt;How to modify the default ITCM/DTCM/OCRAM memory allocations for i.MX RT1064&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Cortex-M4-bare-metal-application-cannot-read-data-from-the/m-p/1337227" target="_self"&gt;Cortex-M4 bare-metal application cannot read data from the shared memory(OCRAM)&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/td-p/911056" target="_self"&gt;What is OCRAM?&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Read-access-to-OCRAM-from-M4-core/m-p/1333836" target="_self"&gt;Read access to OCRAM from M4 core&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Some of these threads are from i.MX processor posts, however they can provide usefull information.&lt;/P&gt;
&lt;P&gt;I'll let you know if we have better documentation regarding your question. I'll look into it.&lt;/P&gt;
&lt;P&gt;Best Regards, Miguel.&lt;/P&gt;</description>
      <pubDate>Mon, 30 Oct 2023 20:29:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1748956#M27360</guid>
      <dc:creator>Miguel04</dc:creator>
      <dc:date>2023-10-30T20:29:06Z</dc:date>
    </item>
    <item>
      <title>Re: iMX RT1170 Shared Memory</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1750168#M27389</link>
      <description>&lt;P&gt;Hi Miguel,&lt;/P&gt;&lt;P&gt;I am using the RAM3 region. Base address is 0x2024000. I write array to this address from CM7 with a pointer. When I switch to CM4 with Debug and read these addresses, I see the data has changed. Except base address's data.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 01 Nov 2023 09:21:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1750168#M27389</guid>
      <dc:creator>BTasdemir</dc:creator>
      <dc:date>2023-11-01T09:21:21Z</dc:date>
    </item>
    <item>
      <title>Re: iMX RT1170 Shared Memory</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1752965#M27463</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/223203"&gt;@BTasdemir&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Are you doing something between writing with CM7 and reading CM4?&lt;/P&gt;
&lt;P&gt;I mean is there any other routines or peripherals that keep executing.&lt;/P&gt;
&lt;P&gt;Regards, Miguel.&lt;/P&gt;</description>
      <pubDate>Mon, 06 Nov 2023 18:05:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1752965#M27463</guid>
      <dc:creator>Miguel04</dc:creator>
      <dc:date>2023-11-06T18:05:56Z</dc:date>
    </item>
    <item>
      <title>Re: iMX RT1170 Shared Memory</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1760382#M27661</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206759"&gt;@Miguel04&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I split the OCRAM area. Im using 0x20338000 address for sharing datas.&amp;nbsp;I write data from M4 core to this address and then I want to read same datas in same address. When I read from M4, I can see that the data has changed&amp;nbsp;but when I read from M7, I cannot see that the data has changed. If I stop the code with a breakpoint, the data is updated.&lt;/P&gt;</description>
      <pubDate>Tue, 21 Nov 2023 05:25:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/iMX-RT1170-Shared-Memory/m-p/1760382#M27661</guid>
      <dc:creator>BTasdemir</dc:creator>
      <dc:date>2023-11-21T05:25:18Z</dc:date>
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