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    <title>topic FlexSPI with EDMA SCK stops in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexSPI-with-EDMA-SCK-stops/m-p/1733837#M27095</link>
    <description>&lt;P&gt;I am using an RT1052 and transferring 1056 byte buffers from FlexSPI to internal/FlexRAM OCRAM using the EDMA through the IP port. I find that the first 266 bytes get sent as quickly as possible (ie the RT1052 doesn't stop SCK). After 266 bytes, SCK stops for 17 periods every 8th byte.&lt;/P&gt;&lt;P&gt;My clocks are:&lt;/P&gt;&lt;P&gt;AHB_CLK_ROOT = 600MHz (from PLL1)&lt;BR /&gt;IPG_CLK_ROOT = 150MHz (IPG_PODF = 3 / divide by 4)&lt;BR /&gt;FLEXSPI_CLK_ROOT = 60MHz (from PLL3[PFD0], PLL3[PFD0] = 360MHz, FLEXSPI_PODF = 5 = div6)&lt;/P&gt;&lt;P&gt;My application is running from FlexRAM DTCM.&lt;/P&gt;&lt;P&gt;The EDMA config for this transfer is:&lt;BR /&gt;srcAddr = 0x402a8100&lt;BR /&gt;destAddr = 0x20222994&lt;BR /&gt;srcTransferSize = kEDMA_TransferSize1Bytes&lt;BR /&gt;destTransferSize = kEDMA_TransferSize1Bytes&lt;BR /&gt;srcOffset = 1&lt;BR /&gt;destOffset = 1&lt;BR /&gt;minorLoopBytes = 8&lt;BR /&gt;majorLoopBytes = 132&lt;/P&gt;&lt;P&gt;It looks like the EDMA is not emptying the IP RX FIFO quickly enough. Is my EDMA configuration incorrect? This is all based on the flexspi_edma example from the SDK.&lt;/P&gt;</description>
    <pubDate>Wed, 04 Oct 2023 16:05:46 GMT</pubDate>
    <dc:creator>gavin5342</dc:creator>
    <dc:date>2023-10-04T16:05:46Z</dc:date>
    <item>
      <title>FlexSPI with EDMA SCK stops</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexSPI-with-EDMA-SCK-stops/m-p/1733837#M27095</link>
      <description>&lt;P&gt;I am using an RT1052 and transferring 1056 byte buffers from FlexSPI to internal/FlexRAM OCRAM using the EDMA through the IP port. I find that the first 266 bytes get sent as quickly as possible (ie the RT1052 doesn't stop SCK). After 266 bytes, SCK stops for 17 periods every 8th byte.&lt;/P&gt;&lt;P&gt;My clocks are:&lt;/P&gt;&lt;P&gt;AHB_CLK_ROOT = 600MHz (from PLL1)&lt;BR /&gt;IPG_CLK_ROOT = 150MHz (IPG_PODF = 3 / divide by 4)&lt;BR /&gt;FLEXSPI_CLK_ROOT = 60MHz (from PLL3[PFD0], PLL3[PFD0] = 360MHz, FLEXSPI_PODF = 5 = div6)&lt;/P&gt;&lt;P&gt;My application is running from FlexRAM DTCM.&lt;/P&gt;&lt;P&gt;The EDMA config for this transfer is:&lt;BR /&gt;srcAddr = 0x402a8100&lt;BR /&gt;destAddr = 0x20222994&lt;BR /&gt;srcTransferSize = kEDMA_TransferSize1Bytes&lt;BR /&gt;destTransferSize = kEDMA_TransferSize1Bytes&lt;BR /&gt;srcOffset = 1&lt;BR /&gt;destOffset = 1&lt;BR /&gt;minorLoopBytes = 8&lt;BR /&gt;majorLoopBytes = 132&lt;/P&gt;&lt;P&gt;It looks like the EDMA is not emptying the IP RX FIFO quickly enough. Is my EDMA configuration incorrect? This is all based on the flexspi_edma example from the SDK.&lt;/P&gt;</description>
      <pubDate>Wed, 04 Oct 2023 16:05:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexSPI-with-EDMA-SCK-stops/m-p/1733837#M27095</guid>
      <dc:creator>gavin5342</dc:creator>
      <dc:date>2023-10-04T16:05:46Z</dc:date>
    </item>
    <item>
      <title>Re: FlexSPI with EDMA SCK stops</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexSPI-with-EDMA-SCK-stops/m-p/1735382#M27138</link>
      <description>&lt;P&gt;Problem was *TransferSize.&amp;nbsp; Example and default is 1Byte which is slow.&amp;nbsp; Using this method:&lt;/P&gt;&lt;P&gt;FLEXSPI_TransferUpdateSizeEDMA(base, &amp;amp;handle, kFLEXSPI_EDMAnSize8Bytes); means that there are no more stalls and FlexSPI operates with maximum possible bandwidth.&lt;/P&gt;</description>
      <pubDate>Sun, 08 Oct 2023 20:52:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/FlexSPI-with-EDMA-SCK-stops/m-p/1735382#M27138</guid>
      <dc:creator>gavin5342</dc:creator>
      <dc:date>2023-10-08T20:52:39Z</dc:date>
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