RT1170 Dual Core Example For CM4 Primary Core

frozen — Fri, 25 Aug 2023 09:04:14 GMT

I need to configure M4 as a primary core, because M4 will handle CAN communication and system will wake up from CAN Interrupt.

There is an app note AN13264 for multicore example and AN13574 for CM4 Primary Core Application.

I have downloaded AN13574SW but there is no buildable project for MCU Xpresso. I can't run it. I need a help to configure memory configurations, predefined macros and etc.

Then I made projects for CM4 and CM7 for MIMXRT1170-EVK. But here I can't debug it, I get an error as below. You can find projects attached.

Target error from Write register: Ep(08). Cannot access core regs when target running.

Another question is about boot core. When change boot core as CM4, could I rechange to use CM7 as boot core ?

MCUXpresso IDE RedlinkMulti Driver v11.7 (Mar 22 2023 09:52:55 - crt_emu_cm_redlink build 13) Found chip XML file in C:/FO-Workspace/BedSideModule/Software/z_M4MASTER/Debug\MIMXRT1176xxxxx.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. ============= SCRIPT: RT1170_connect_M7_wake_M4.scp ============= RT1170 Connect M7 and Wake M4 Script DpID = 6BA02477 APID = 0x84770001 Setting M4 spin code Setting M4 clock Resetting M4 core View cores on the DAP AP DpID = 6BA02477 TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003 TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003* ============= END SCRIPT ======================================== Probe Firmware: CMSIS-DAP (ARM) Serial Number: 024400003ac6ec1b00000000000000000000000097969905 VID:PID: 0D28:0204 USB Path: \\?\hid#vid_0d28&pid_0204&mi_03#9&db0cf90&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030} Using memory from core 1 after searching for a good core debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 1 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000C24. Info: <None> Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core ROM 1 E0043000: CID B105900D PID 04001BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router ROM 1 E0042000: CID B105900D PID 04005BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT CM4 Rev. 4.0 LMEM NXP: MIMXRT1176xxxxx DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1170_SFDP_QSPI.cfx Image 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Mar 21 2023 13:05:46' Opening flash driver MIMXRT1170_SFDP_QSPI.cfx Sending VECTRESET to run flash driver Flash variant 'iMXRT1170_SFDP_FlexSPI1_A_QSPI Mar 21 2023 13:05:46' detected (16MB = 256*64K at 0x8000000) Closing flash driver MIMXRT1170_SFDP_QSPI.cfx Connected: was_reset=true. was_stopped=false Awaiting telnet connection to port 3335 ... GDB nonstop mode enabled ============= SCRIPT: RT1170_reset.scp ============= SYSTEM Reset DpID = 6BA02477 TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003 TAP 0: 6BA02477 AP 1: APID: 24770011 ROM Table: E00FF003 TAP 0: 6BA02477 AP 2: APID: 54770002 ROM Table: 00000002 APID = 0x84770001 Setting M4 spin code Setting M4 clock Resetting M4 core Releasing M4 View cores on the DAP AP DpID = 6BA02477 TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003 TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003* R15 = 0x00223104 Vector table SP/PC is the reset context. PC = 0x300024C9 SP = 0x20040000 XPSR = 0x01000000 VTOR = 0x30002000 Set DEMCR = 0x010007F1 ============= END SCRIPT =========================== Target error from Write register: Ep(08). Cannot access core regs when target running. GDB stub (C:\NXP\MCUXpressoIDE_11.7.1_9221\ide\plugins\com.nxp.mcuxpresso.tools.bin.win32_11.7.1.202303220859\binaries\crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB.

Re: RT1170 Dual Core Example For CM4 Primary Core

RaRo — Fri, 25 Aug 2023 20:22:14 GMT

Hello @frozen,

As you mentioned you could follow the AN13574. i.MX RT1170 CM4 Primary Core Application. to change the primary core to CM4, but for that you need to burn fuses, as mentioned in the application note as follows: "By fusing 960[12], we can switch to CM4 primary core and then the system boots from CM4 core."

Nonetheless, once you switch to CM4 as Primary Core Application you will not longer be able to change it again to CM7. As the readme in AN13574SW's example_iar mentions: "Keep in mind that this operation is not reversible, i.e. once switching to Cortex-M4 entry it is not possible to change it back to Cortex-M7 entry."

Best regards, Raul.

i.MX RT Crossover MCUsのトピックRe: RT1170 Dual Core Example For CM4 Primary Core

RT1170 Dual Core Example For CM4 Primary Core

Re: RT1170 Dual Core Example For CM4 Primary Core