topic Re: 1061 fuse configuration in i.MX RT Crossover MCUs

1061 fuse configuration

tmerics — Wed, 16 Aug 2023 14:09:16 GMT

I have a custom rt1061 board. I cannot get it to boot from external flash. It always goes to the bootloader. I used the MCU boot utility to look at the fuses. For 0x460 I read an 0x00000008 for a new part before I program the boot from fuses bit (0x00000010 in 0x460). When I read this location on a 1062 EVK I see 0x00000000. Looks like the bit 0x80 disables booting from external memory. This bit is set on the 1064 which has internal flash.

I also programmed the boot from fuses bit on one board and it won't try to boot from the flash chip.

Why would this fuse be programmed with a brand new part?

Re: 1061 fuse configuration

mjbcswitzerland — Wed, 16 Aug 2023 21:59:38 GMT

#define eFUSE_CFG1 0x460 // locked by BOOT_CFG_LOCK #define uFUSE_BOOT_CFG1_SEC_CONFIG_OPEN (0x00000000)// allows any program image, even if authentication fails (shipped value) #define uFUSE_BOOT_CFG1_SEC_CONFIG_CLOSED (0x00000002)// the program image executes only if authenticated #define uFUSE_BOOT_CFG1_BOOT_FREQ_396_132MHz (0x00000000)// boot frequency 396MHz core and 132MHz bus #define uFUSE_BOOT_CFG1_BOOT_FREQ_528_132MHz (0x00000004)// boot frequency 528MHz core and 132MHz bus #define uFUSE_BOOT_CFG1_DIR_BT_DIS (0x00000008)// disables the NXP reserved mode - must be set for the secure boot #define uFUSE_BOOT_CFG1_BT_FUSE_SEL (0x00000010)// in internal boot mode (BOOT_MODE[1:0] = 10) this fuse determines whether the GPIO input override bits in SBMR are taken or not #define uFUSE_BOOT_CFG1_FORCE_COLD_BOOT (0x00000020)// force cold boot when core comes out of reset - reflected in SBMR register of SRC (higher level of security) #define uFUSE_BOOT_CFG1_BEE_KEY0_SEL_REGISTER (0x00000000)// take the AES key selection for BEE_KEY0 from register (default) #define uFUSE_BOOT_CFG1_BEE_KEY0_SEL_SW_GP2 (0x00003000)// take the AES key selection for BEE_KEY0 from SW-GP2 #define uFUSE_BOOT_CFG1_BEE_KEY1_SEL_REGISTER (0x00000000)// take the AES key selection for BEE_KEY1 from register (default) #define uFUSE_BOOT_CFG1_BEE_KEY1_SEL_SW_GP2 (0x0000c000)// take the AES key selection for BEE_KEY1 from SW-GP2 #define uFUSE_BOOT_CFG1_FORCE_INTERNAL_BOOT (0x00010000)// BT_MODE pins are ignore and the boot mode is forced to internal boot #define uFUSE_BOOT_CFG1_SDP_DISABLE (0x00020000)// disable serial download support #define uFUSE_BOOT_CFG1_SDP_READ_DISABLE (0x00040000)// serial download read register is disabled #define uFUSE_BOOT_CFG1_DAP_SJC_SWD_SEL_SWD (0x00000000)// DAP works in SWD mode (default) #define uFUSE_BOOT_CFG1_DAP_SJC_SWD_SEL_JTAG (0x00080000)// DAP works in JTAG mode #define uFUSE_BOOT_CFG1_SJC_DISABLE (0x00100000)// disable secure JTAG controller #define uFUSE_BOOT_CFG1_WDOG_ENABLE (0x00200000)// enable the watchdog #define uFUSE_BOOT_CFG1_JTAG_SMODE_JTAG (0x00000000)// normal JTAG mode enabled (default) #define uFUSE_BOOT_CFG1_JTAG_SMODE_SECURE (0x00400000)// secured JTAG mode enabled #define uFUSE_BOOT_CFG1_JTAG_SMODE_NO_DEBUG (0x00c00000)// no JTAG debug mode #define uFUSE_BOOT_CFG1_DLL_ENABLE (0x01000000)// enable DLL for SD/eMMC #define uFUSE_BOOT_CFG1_NAND_ECC_DISABLE (0x02000000)// disable NAND ECC #define uFUSE_BOOT_CFG1_KTE (0x04000000)// kill trace enable #define uFUSE_BOOT_CFG1_JTAG_HEO (0x08000000)// HAB JTAG enable is overridden #define uFUSE_BOOT_CFG1_PWR_STABLE_CYCLE_SELECTION (0x20000000) #define uFUSE_BOOT_CFG1_SD_PWR_CYCLE_SELECTION_MASK (0xc0000000)

How are your Mode 00 and 01 pins ?

Do you measure pulses the CS line of the external flash? If the configuration can't be read correctly from the Flash it will always go to the ISP mode.

Regards

Mark

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Re: 1061 fuse configuration

tmerics — Fri, 18 Aug 2023 16:07:39 GMT

One of the questions I had was the fact that the uFUSE_BOOT_CFG1_DIR_BT_DIS fuse is programmed on a brand new processor. Is this normal?

I also am not getting any chip selects when I download firmware via jlink or when I reset the processor. I was able to modify the board to ground all the config GPIO pins as on the EVK. I tried using internal boot mode (10 on boot mode pins) and it still does not try to access the flash device. I'm using the same flexspi port / pins as the EVK board.

I also programmed the boot from fuses bit on one board. Still no accesses to the flash chip.

Re: 1061 fuse configuration

mjbcswitzerland — Fri, 18 Aug 2023 16:33:02 GMT

I have some products based on the 1062 (1061 with LCD) and read out these eFUSES (I don't program them):

FUSEs
======
LOCK
0x40128003
CFG
0x614ebcf7
0x1024a9d7 <--- CFG1
0x5001004e
0x00420002
0x00000000
0x00000008
0x00000000
MEM
0x00000000
0x00009400
0x000000db
0x00000000
0x00000000
ANALOG
0x00000000
0x53c4dc5f
0x00000000
SRK
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
SJC
0x00000000
0x00000000
MAC
0x00000000
0x00000000
0x00000000
GP
0x00000000
0x00000000
SW GP
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
MISC
0x00000040
0x00000000
REVOKE
0x00000000
PATCH
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
GP3
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000

Regards

Mark

Re: 1061 fuse configuration

mjbcswitzerland — Fri, 18 Aug 2023 22:17:33 GMT

Hi

The correct Mode setting is:
Normal Boot: Mode 00 = '0' / Mode 01 = '1'

When you load code via JTAG it depends where you are loading it to whether it uses the CS line.

After every reset the BOOT LOADER (when in correct mode) will read form the external Flash and therefore CS line pulses must be visible.

Regards

Mark