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    <title>topic Invalid data in first 2 bytes of flash AHB read on RT1176 in i.MX RT Crossover MCUs</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Invalid-data-in-first-2-bytes-of-flash-AHB-read-on-RT1176/m-p/1696190#M26129</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am currently trying to read a page of test data from the external flash with the RT1176. I have written the following content to flash using the FlexSPI interface:&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="Screenshot 2023-08-01 at 10.03.17 am.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/234420iDEE8FCD1C2B773EB/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2023-08-01 at 10.03.17 am.png" alt="Screenshot 2023-08-01 at 10.03.17 am.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;I have validated that this data is written correctly and persists as expected. However, when I try to read this data using AHB I am getting invalid data where the first two bytes are always CC CC. This causes the data to be offset and results in the last two bytes of the stored flash data to be ignored (see below).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="Screenshot 2023-08-01 at 10.06.37 am.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/234421i029007F24D20EDD4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2023-08-01 at 10.06.37 am.png" alt="Screenshot 2023-08-01 at 10.06.37 am.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="Screenshot 2023-08-01 at 10.07.10 am.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/234422i3247C795E0A84E14/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2023-08-01 at 10.07.10 am.png" alt="Screenshot 2023-08-01 at 10.07.10 am.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;It appears that are the start of every page there is two bytes that contain CC CC despite there being no such data in the flash. I have made sure to clean and invalidate the D-Cache at the range I am reading from prior to performing a memcpy. I am using the following code to perform the read operation:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;int main(void) {

    /* Init board hardware. */
    BOARD_ConfigMPU();
    BOARD_InitBootPins();
    BOARD_InitBootClocks();
    BOARD_InitBootPeripherals();
#ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL
    /* Init FSL debug console. */
    BOARD_InitDebugConsole();
#endif

    // SCB_EnableDCache();

    FLASH_Initialise(FLEXSPI1);
    FLASH_EnableQuadMode(FLEXSPI1);

    DCACHE_CleanInvalidateByRange(0x30140000, 256);
    // DCACHE_InvalidateByRange(0x30140000, 256);
    uint8_t data[256] = { 0xFF };

    memcpy(data, (void *)0x30140000, 256);

    PRINTF("Data: \r\n");
    for(uint16_t i = 0; i &amp;lt; 256; i++) {
        if(i % 20 == 0) PRINTF("\r\n");
        PRINTF("%02X ", data[i]);
    }

    for( ;; ) __asm__("nop"); // Infinite loop
    PRINTF("Well **bleep** \r\n");
    return 0; // This should never be reached
}&lt;/LI-CODE&gt;&lt;LI-CODE lang="c"&gt;void FLASH_Initialise(FLEXSPI_Type *base) {
    flexspi_config_t config;

    STK_DisableDCache(); // Disable D-Cache if exists

    flexspi1_clock_init();

    FLEXSPI_GetDefaultConfig(&amp;amp;config);
    config.ahbConfig.enableAHBPrefetch = true;
    config.ahbConfig.enableAHBBufferable = true;
    config.ahbConfig.enableAHBCachable = true;
    config.ahbConfig.enableReadAddressOpt = true;
    config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
    FLEXSPI_Init(base, &amp;amp;config);

    FLEXSPI_SetFlashConfig(base, &amp;amp;deviceConfig, kFLEXSPI_PortA1);
    FLEXSPI_UpdateLUT(base, 0, flashLookupTable, FLASH_LUT_SIZE);
    FLEXSPI_SoftwareReset(base);

    STK_EnableDCache(); // Enable D-Cache if exists
}&lt;/LI-CODE&gt;&lt;LI-CODE lang="c"&gt;status_t FLASH_EnableQuadMode(FLEXSPI_Type *base) {
    flexspi_transfer_t transfer;
    status_t status;
    uint32_t writeVal = FLASH_QUAD_ENABLE;

    status = FLASH_EnableWrite(base, 0);

    if(status != kStatus_Success) return status;
    
    transfer.deviceAddress = 0;
    transfer.port = kFLEXSPI_PortA1;
    transfer.cmdType = kFLEXSPI_Write;
    transfer.SeqNumber = 1;
    transfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
    transfer.data = &amp;amp;writeVal;
    transfer.dataSize = 1;

    status = FLEXSPI_TransferBlocking(base, &amp;amp;transfer);
    if(status != kStatus_Success) return status;

    status = FLASH_WaitForBusFinish(base);
    FLASH_ClearBuffer(base);

    return status;
}&lt;/LI-CODE&gt;&lt;LI-CODE lang="c"&gt;static inline void flexspi1_clock_init(void) {
    CLOCK_SetRootClockDiv(kCLOCK_Root_Flexspi1, 2);
    CLOCK_SetRootClockMux(kCLOCK_Root_Flexspi1, 0);
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any ideas as to what could be causing this?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Jon&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Flash chip being used: &lt;SPAN&gt;MT25QU512ABB&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SoM being used: TQMa117xL&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 01 Aug 2023 00:17:13 GMT</pubDate>
    <dc:creator>JonMcLeanSMC</dc:creator>
    <dc:date>2023-08-01T00:17:13Z</dc:date>
    <item>
      <title>Invalid data in first 2 bytes of flash AHB read on RT1176</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Invalid-data-in-first-2-bytes-of-flash-AHB-read-on-RT1176/m-p/1696190#M26129</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am currently trying to read a page of test data from the external flash with the RT1176. I have written the following content to flash using the FlexSPI interface:&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="Screenshot 2023-08-01 at 10.03.17 am.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/234420iDEE8FCD1C2B773EB/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2023-08-01 at 10.03.17 am.png" alt="Screenshot 2023-08-01 at 10.03.17 am.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;I have validated that this data is written correctly and persists as expected. However, when I try to read this data using AHB I am getting invalid data where the first two bytes are always CC CC. This causes the data to be offset and results in the last two bytes of the stored flash data to be ignored (see below).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="Screenshot 2023-08-01 at 10.06.37 am.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/234421i029007F24D20EDD4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2023-08-01 at 10.06.37 am.png" alt="Screenshot 2023-08-01 at 10.06.37 am.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="Screenshot 2023-08-01 at 10.07.10 am.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/234422i3247C795E0A84E14/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2023-08-01 at 10.07.10 am.png" alt="Screenshot 2023-08-01 at 10.07.10 am.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;It appears that are the start of every page there is two bytes that contain CC CC despite there being no such data in the flash. I have made sure to clean and invalidate the D-Cache at the range I am reading from prior to performing a memcpy. I am using the following code to perform the read operation:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;int main(void) {

    /* Init board hardware. */
    BOARD_ConfigMPU();
    BOARD_InitBootPins();
    BOARD_InitBootClocks();
    BOARD_InitBootPeripherals();
#ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL
    /* Init FSL debug console. */
    BOARD_InitDebugConsole();
#endif

    // SCB_EnableDCache();

    FLASH_Initialise(FLEXSPI1);
    FLASH_EnableQuadMode(FLEXSPI1);

    DCACHE_CleanInvalidateByRange(0x30140000, 256);
    // DCACHE_InvalidateByRange(0x30140000, 256);
    uint8_t data[256] = { 0xFF };

    memcpy(data, (void *)0x30140000, 256);

    PRINTF("Data: \r\n");
    for(uint16_t i = 0; i &amp;lt; 256; i++) {
        if(i % 20 == 0) PRINTF("\r\n");
        PRINTF("%02X ", data[i]);
    }

    for( ;; ) __asm__("nop"); // Infinite loop
    PRINTF("Well **bleep** \r\n");
    return 0; // This should never be reached
}&lt;/LI-CODE&gt;&lt;LI-CODE lang="c"&gt;void FLASH_Initialise(FLEXSPI_Type *base) {
    flexspi_config_t config;

    STK_DisableDCache(); // Disable D-Cache if exists

    flexspi1_clock_init();

    FLEXSPI_GetDefaultConfig(&amp;amp;config);
    config.ahbConfig.enableAHBPrefetch = true;
    config.ahbConfig.enableAHBBufferable = true;
    config.ahbConfig.enableAHBCachable = true;
    config.ahbConfig.enableReadAddressOpt = true;
    config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
    FLEXSPI_Init(base, &amp;amp;config);

    FLEXSPI_SetFlashConfig(base, &amp;amp;deviceConfig, kFLEXSPI_PortA1);
    FLEXSPI_UpdateLUT(base, 0, flashLookupTable, FLASH_LUT_SIZE);
    FLEXSPI_SoftwareReset(base);

    STK_EnableDCache(); // Enable D-Cache if exists
}&lt;/LI-CODE&gt;&lt;LI-CODE lang="c"&gt;status_t FLASH_EnableQuadMode(FLEXSPI_Type *base) {
    flexspi_transfer_t transfer;
    status_t status;
    uint32_t writeVal = FLASH_QUAD_ENABLE;

    status = FLASH_EnableWrite(base, 0);

    if(status != kStatus_Success) return status;
    
    transfer.deviceAddress = 0;
    transfer.port = kFLEXSPI_PortA1;
    transfer.cmdType = kFLEXSPI_Write;
    transfer.SeqNumber = 1;
    transfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
    transfer.data = &amp;amp;writeVal;
    transfer.dataSize = 1;

    status = FLEXSPI_TransferBlocking(base, &amp;amp;transfer);
    if(status != kStatus_Success) return status;

    status = FLASH_WaitForBusFinish(base);
    FLASH_ClearBuffer(base);

    return status;
}&lt;/LI-CODE&gt;&lt;LI-CODE lang="c"&gt;static inline void flexspi1_clock_init(void) {
    CLOCK_SetRootClockDiv(kCLOCK_Root_Flexspi1, 2);
    CLOCK_SetRootClockMux(kCLOCK_Root_Flexspi1, 0);
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any ideas as to what could be causing this?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Jon&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Flash chip being used: &lt;SPAN&gt;MT25QU512ABB&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SoM being used: TQMa117xL&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 01 Aug 2023 00:17:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Invalid-data-in-first-2-bytes-of-flash-AHB-read-on-RT1176/m-p/1696190#M26129</guid>
      <dc:creator>JonMcLeanSMC</dc:creator>
      <dc:date>2023-08-01T00:17:13Z</dc:date>
    </item>
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