topic Re: LPADC1 Differential mode in i.MX RT Crossover MCUs

LPADC1 Differential mode

Max83 — Wed, 29 Mar 2023 09:51:16 GMT

Dear support,

I'm designing a custom board based on IMXRT1176 and I have to configure LPADC1 to take a differential reading through pins GPIO_AD_06 (A,1_0) and GPIO_AD_07 (B, 1_0). I'm using the MCUXpresso Config Tool under the peripheral section to add a new command. The tool allow me to select Channel sample mode=Differential mode (A as plus, B as minus) and Channel number=A, 1_0 » [N13] GPIO_AD_06 and B, 1_0 » [T17] GPIO_AD_07. The problem is that I have a warning that say Signal channel 1B is not routed. On the Pin section of the tool the LPADC1 is already selected for the pins GPIO_AD_06 and GPIO_AD_07.

Why I have this warning? Am I doing something wrong? Herewith enclosed a screenshot of the tool.

Thank you in advance for the support.

Kind regards,

Max83

Re: LPADC1 Differential mode

jingpan — Thu, 30 Mar 2023 02:56:45 GMT

Hi @Max83 ,

I tested both on MCUXpresso IDE and config tool. But I didn't see the warning. What's your tool version. I found the item name in Cahhenl number menu is different.

jingpan_1-1680144950453.png

Have you set ADC pins in pin config window like this?

jingpan_0-1680144928185.png

Regards,

Jing

Re: LPADC1 Differential mode

Max83 — Thu, 30 Mar 2023 06:52:18 GMT

Dear Jing,

thank you for your reply.

I'm using MCUXpresso Config Tools Pins version 13 and Peripheral Version 12.0. The SDK in in version 2.13.1.

Yesterday I did some tests with the MCUXpresso IDE and I can confirm that the Channel number conformed with your one. But also in this tool I have the same problem.

I have discovered that the warning appears as soon as in the Peripheral Signals of the Pins tool I enable OTG1_ID on pin GPIO_AD_09. The funny thing is that when I rout pin OTG1_ID on pin GPIO_AD_09, the LPADC1 peripheral generate the warning for every conversion command that involve the B part of the ADC. (e.g. Channel sample mode = Single end mode, using B and Channel number=B, 1_0 » [T17] USB_OTG2_PWR/WL_DEV_WAKE/U354[10]/J10[2] or B, 1_2 » [P16] USB_OTG1_OC/U26[A2]/J26[4] or B, 1_3 » [L12] SPDIF_SR_CLK/ANATOP_32K_OUT/J26[8] etc....

I'm starting to think there is a bug in this part of the tool. The generated code per the pin mux looks correct to me (see below).

What's your opinion?

Kind regards,

Massimo

void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */

IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05, /* GPIO_AD_06 is configured as GPIO_MUX3_IO05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06, /* GPIO_AD_07 is configured as GPIO_MUX3_IO06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID, /* GPIO_AD_09 is configured as USBPHY1_OTG_ID */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable, Highz
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable, Highz
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}

Re: LPADC1 Differential mode

jingpan — Mon, 03 Apr 2023 02:53:48 GMT

Hi @Max83 ,

Yes, it seems like a bug. I'll report it. You can ignore the warning message.

Regards,

Jing

Re: LPADC1 Differential mode

Max83 — Mon, 03 Apr 2023 06:45:18 GMT

Hi @jingpan ,

thank you for your reply. May you tell me where I can find chip related informations? For instance, is there any document that specify the pin couple that I have to use for a differential voltage conversion? I can't find this information in the reference manual.

Kind regards,

Massimo

Re: LPADC1 Differential mode

jingpan — Tue, 04 Apr 2023 03:07:47 GMT

Hi @Max83 ,

That is in datasheet.

https://www.nxp.com/docs/en/data-sheet/IMXRT1170CEC.pdf

Regards,

Jing

Re: LPADC1 Differential mode

Max83 — Thu, 06 Apr 2023 11:51:03 GMT

Ok, thank you very much for the support.

Kind regards,

Massimo