Controlling FlexIO parallel transfer

CktDesigner — Mon, 27 Mar 2023 01:41:23 GMT

I'm using FLEXIO2 to shift out 4-bit values. I'm using MCUXpresso and SDK version 2.13.0 with iMXRT1060-EVKB

I've been able to get 4-bit values to shift out using a test case. The test has all shifters (SHIFT 7-0) chained together and DMA transfers 32 bytes per access (filling all 8 Shiftbufs). The upper 8 bits of the Timer CMP register are set to 127 (since there are 8 "4-bit items" per 32-bit word and 8 words fetched). The trigger is set as Shifter7. If I set the major loop to 3, then 384 4-bit values are shifted out and the shifter stops (as expected).

But I haven't been able scale this to my needs... My application needs to shift 133 4-bit values from one location, then shift another set of 133 from a different location, etc.

133 4-bit values requires 16+ 32-bit words, so I rounded the buffer size up to 18 32-bit words. Since the DMA is programmed as minor/major loops, I decided to make the minor fetch access 2 32-bit words, so the major loop is executed 9 times. Since the minor loop is 2 32-bit words, I only enabled FlexIO shifters 1 and 0. and set the trigger from shifter 1.

However, this doesn't produce the desired result. So I changed the FlexIO shifter/buffer to use all 8 shifters chained together, and this still didn't work.

If I set things up similar to the test case, the 4-bit values come out, but I can't stop at 133 values.

Some questions:

1) (CMP[15:8] +1)/2 is the number of "bits" per word in the documentation. But it seems that it is really the number of shift items per DMA (minor) fetch?

2) Should the number of shifter/shiftbuf registers chained together match the size of the DMA (minor) fetch? Or do they operate independently? (ie.

3) It seems that controlling the number of shifts is a combination of the CMP value and the number of minor/major DMA fetches... Is there a better way to control the number of items shifted out of FlexIO?

4) How can you determine when the shifting has completed (so a new address can be loaded and the shifting restarted)? I see both shift and DMA interrupts, but when watching on a logic analyzer, they don't appear at the end of shifting... Is there some other interrupt that can be raised when the shifting has completed?

5) Is there a better way to do this?

6) Another version of my application requires 32-bit values be shifted out. I know how to expand the buffers/pins to provide the 32-bit data, but that uses all of the available pins that FLEXIO2 has allocated. Is there a way to route the Timer output to some different pin (for a clock)?

Thanks!!

topic Controlling FlexIO parallel transfer in i.MX RT Crossover MCUs

Controlling FlexIO parallel transfer