https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Noncacheable-data-for-drivers/m-p/1551719#M22434 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206562">@embeddman</a>&nbsp;,<BR />Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.<BR />1) Should these two structures be located in non cacheable region or it doesn't matter?<BR />-- It doesn't matter.<BR />Have a great day,<BR />TIC</P> <P>-------------------------------------------------------------------------------<BR />Note:<BR />- If this post answers your question, please click the "Mark Correct" button. Thank you!</P> <P>&nbsp;</P> <P>- We are following threads for 7 weeks after the last post, later replies are ignored<BR />Please open a new thread and refer to the closed one, if you have a related question at a later point in time.<BR />-------------------------------------------------------------------------------</P> Thu, 10 Nov 2022 07:18:47 GMT jeremyzhou 2022-11-10T07:18:47Z https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Noncacheable-data-for-drivers/m-p/1550997#M22416 <P>Hello!</P><P>I'm using lpuart and lpspi drivers with EDMA. For applying EDMA, buffers must be located in noncacheable regions of RAM with&nbsp;<STRONG>AT_NONCACHEABLE_SECTION_INIT</STRONG> macro. But in lpspi example&nbsp;<STRONG>lpspi_master_edma_handle_t</STRONG> structure is also located in this section unlike&nbsp;<STRONG>lpuart_edma_handle_t&nbsp;</STRONG>structure which is not located in noncacheable region. Should these two structures be located in noncacheable region or it doesn't matter?</P> Wed, 09 Nov 2022 10:40:38 GMT https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Noncacheable-data-for-drivers/m-p/1550997#M22416 embeddman 2022-11-09T10:40:38Z https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Noncacheable-data-for-drivers/m-p/1551719#M22434 <P>Hi <a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206562">@embeddman</a>&nbsp;,<BR />Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.<BR />1) Should these two structures be located in non cacheable region or it doesn't matter?<BR />-- It doesn't matter.<BR />Have a great day,<BR />TIC</P> <P>-------------------------------------------------------------------------------<BR />Note:<BR />- If this post answers your question, please click the "Mark Correct" button. Thank you!</P> <P>&nbsp;</P> <P>- We are following threads for 7 weeks after the last post, later replies are ignored<BR />Please open a new thread and refer to the closed one, if you have a related question at a later point in time.<BR />-------------------------------------------------------------------------------</P> Thu, 10 Nov 2022 07:18:47 GMT https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Noncacheable-data-for-drivers/m-p/1551719#M22434 jeremyzhou 2022-11-10T07:18:47Z