i.MX RT Crossover MCUsのトピックRe: RT1050 SDRAM clock configuration

RT1050 SDRAM clock configuration

joshuasakwa — Thu, 31 May 2018 21:12:07 GMT

I couldn't find a note on how to configure the clock for specific SDRAM part, but noticed that in in the SEMC example there are a couple of clues:

a define: EXAMPLE_SEMC_CLK_FREQ
a comment: /* Set semc clock to 132Mhz */

if EXAMPLE_SEMC_CLK_FREQ is printed the value is: 109241376 -- I was anticipating 132MHz (based on the comment and the functionality described in the application note: https://www.nxp.com/docs/en/application-note/AN12077.pdf)

Based on experimentation with the value 'N' passed as the second argument to: CLOCK_SetDiv(kCLOCK_SemcDiv, N) -- where N ranges from 1..7, EXAMPLE_SEMC_CLK_FREQ ranges from: 163862064..40965516

What is the actual clock speed configured by default in the SEMC example (132MHz or 109.2MHz)?
Does the 109.2MHz value indicate that the core clock is not 600MHz?
Does this correspond to the clocking of the SDRAM at 109.2MHz (or 132) -- not 167MHz as reported in the EVK user guide?
What are the acceptable range of values for kCLOCK_SemcDiv?
If the value of kCLOCK_SemcDiv is modified from the default, does that change the units of the sdramconfig data structure passed to SEMC_ConfigureSDRAM, or are these units scaled automatically?
the math: "sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);" rounds down, should I be concerned that the setting might be too aggressive?

Many thanks in advance!

Re: RT1050 SDRAM clock configuration

weidong_sun — Fri, 01 Jun 2018 04:19:07 GMT

Hello Joshua,

See the link, please!

https://community.nxp.com/docs/DOC-340813

After understanding how to configure registers related to SDRAM clock, go back to configure it in SDK.

Have a nice day!

TIC weidong sun

Re: RT1050 SDRAM clock configuration

joshuasakwa — Fri, 01 Jun 2018 16:44:12 GMT

Thanks TIC -- this is great information! I will study it.

Re: RT1050 SDRAM clock configuration

joshuasakwa — Fri, 01 Jun 2018 21:44:03 GMT

Hello Wigros,

I parsed out the register values, and followed the math in the Clock Config note that you forwarded. I arrive at the same 109.2 MHz clock value that was computed by the MCU API functions. To confirm my understanding, a few follow up questions:

1. does this mean that 109.2MHz is the clock being applied to the SDRAM?

2. is it safe to change these various clock dividers to arrive at a different frequency, and if so what is the acceptable range?

3. the math: "sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);" rounds down, should I be concerned that the setting might be too aggressive?

Thanks again for your help!

Joshua