topic Re: SEMC SRAM Interface Questions in i.MX RT Crossover MCUs

SEMC SRAM Interface Questions

gcary — Tue, 29 Jan 2019 20:12:52 GMT

I'm going to interface an FPGA to the i.MX RT1062 using the SEMC, operating in SYNC SRAM ADMUX 16-bit mode. I need to make sure I choose the correct pins before I make my PCB.

Why does the documentation use the term "PSRAM" in some places and "SRAM" in others? Is SRAM a subset of PSRAM? For example, in the table in "24.5.3 Pin Mux in SEMC", the "CRE" bit would only apply to PSRAM and I would not need it for the FPGA. I also wouldn't need the "Column Address bit width" bits in register SRAMCR0. All I want is the ability to burst multiple words in a single bus cycle (determined by BL bits in SRAMCR0, which ranges from 1 to 64).

I'm very confused about the chip selects. Section 24.2.2 describes memory regions, of which SRAM is Region #6. Note that Figure 23-1 is likely in error since it incorrectly shows the wrong CS signals for each type of memory. Section "24.5.3 Pin Mux in SEMC" shows "SEMC_ADDR[8]" as being CS6, which I believe is the CE# signal shown in the timing diagrams. It is selected via IOCR.MUX_A8. Is this CE signal valid for any CS signal? For example, if both SEMC_CSX[0] and SEMC_CSX[1] were enabled on the A24 and A25 pins, the CE# signal would activate when either SEMC_CSX memory region was accessed? This is best described with a picture. Is this correct?

Here are screenshots of the timing diagrams that apply to my intended usage of the SEMC:

Why is cke shown in the timing diagrams? The reference manual says it only applies to SDRAM.

Is "D0", "D1", etc. Data Word 0, Data Word 1, etc.? It is confusing to use the same nomenclature as the data bits. It would be better to say something like "DW0", "DW1", etc. (assuming I'm correct in my understanding). Are 8 words shown as an example, but the range of possibilities is anywhere from 1 to 64?

Is the DQS signal required?

What is dqse?

Is ipg_clk available on a pin as well as CLK?

Thank you for your help.

Greg

Re: SEMC SRAM Interface Questions

Hui_Ma — Wed, 30 Jan 2019 06:30:52 GMT

Hi Greg,

I am checking with this thread.

First, about PSRAM (parallel SRAM) relationship with SRAM, I think PSRAM belongs to SRAM.

SRAM includes serial SRAM and PSRAM.

PSRAM is subset of SRAM.

BTW: For this thread includes many questions, I will answer in following posts.

Thanks for the understanding.

best regards,

Mike

Re: SEMC SRAM Interface Questions

gcary — Wed, 30 Jan 2019 06:51:20 GMT

Thanks Mike. I realize there were a lot of questions in there. Thank you for tackling them!

I always knew PSRAM to be PseudoSRAM, a DRAM device that has internal refresh and an external interface more like SRAM. On page 1567 of the 1060 reference manual is the following:

I did not know what CRE was, so I downloaded a data sheet from a manufacturer of PsuedoSRAM, and in their data sheet was a signal named CRE. Here is a link to the datasheet. On page 6 it says that it stands for "Control Register Enable".

http://www.winbond.com/resource-files/w956d6hb_datasheet_pkg_a01-003_20130529.pdf

Best Regards,

Greg

Re: SEMC SRAM Interface Questions

Hui_Ma — Wed, 30 Jan 2019 07:22:47 GMT

Hi,

About the SRAM chip select, the SRAM read/write timing diagrams CE# only related to SEMC_ADDR[8] pin.

The CE# only available when access Region #6 memory range.

Have a great day,
Mike

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Re: SEMC SRAM Interface Questions

Hui_Ma — Wed, 30 Jan 2019 07:36:32 GMT

Hi,

About SRAM read/write in SYNC mode timing diagram, D[0:7] should be data bit.

It only shows one byte during read/write operation.

DQS signal is required.

dqse is module internal signal doesn't output to external SRAM, which is also suitable with ipg_clk.

Have a great day,
Mike

Re: SEMC SRAM Interface Questions

gcary — Wed, 30 Jan 2019 21:41:15 GMT

I found some information that supports the definition of PSRAM as PsuedoSRAM:

https://en.wikipedia.org/wiki/Dynamic_random-access_memory#PSRAM

What is the CRE signal for?

Regards,

Greg

Re: SEMC SRAM Interface Questions

gcary — Wed, 30 Jan 2019 21:44:32 GMT

Hi Mike,

How do SEMC_CSX[0], SEMC_CSX[1], SEMC_CSX[2], and SEMC_CSX[3] differ from CE# on the SEMC_ADDR[8] pin?

Thanks,

Greg

Re: SEMC SRAM Interface Questions

gcary — Wed, 30 Jan 2019 22:04:44 GMT

Hi Mike,

I respectfully disagree that the timing diagram shows just one byte being transferred. Apply the same reasoning to Figure 24-57 "SRAM Read in ASYNC mode (ADMUX)". In that diagram you would conclude that just one bit is transferred per bus cycle. There is no way that is the case. If it were, SPI would have greater bandwidth. I think you have proven my point that the documentation is misleading by calling it "D0", "D1", etc. Very bad names. Perhaps "W0", "W1", etc. would be better, since "DW0" is kind of long. The bus width could be 8 bits or 16 bits, which is why it should be called "W0" for "Word0".

I apologize if I am wrong, but I am pretty sure that the performance enhancement of the SYNC bus over ASYNC bus is that a new 8 or 16-bit word can be transferred per clock cycle. Assuming this is the case, how do I set up transfers of this nature? Is DMA required?

Thanks,

Greg

Re: SEMC SRAM Interface Questions

gcary — Fri, 01 Feb 2019 05:23:13 GMT

I don't know how I missed it before, but on page 28 of the 1060 Reference Manual it says that PSRAM is Pseudo-Static Random Access Memory. I also found information about it in i.MX6 documentation.

Re: SEMC SRAM Interface Questions

Hui_Ma — Fri, 01 Feb 2019 07:29:01 GMT

Yes, you are right.

The PSRAM is Pseudo-Static Random Access Memory.

Please check below description about CRE signal function.

It was abstracted from Micron TN-45-30: PSRAM 101: An Introduction to Micron PSRAM - DigChip.

CRE signal used to access configuration register.

Thank you for the attention.

best regards,

Mike

Re: SEMC SRAM Interface Questions

Hui_Ma — Fri, 01 Feb 2019 07:41:29 GMT

Hi Greg,

The timing diagram does make confusion.

The SEMC supported SRAM interface with 8/16 bit data width(mode).

If using 8 bit data width, the D0 should be one byte.

If using 16bit data width, the D0 should be one word (two bytes).

From SRAM control register 0 (SRAMCR0) burst length up to 64 bytes.

The SRAM read/write in SYNC mode figures are just an example for 8 or 16 bytes access.

Thanks for the attention.

Have a great day,
Mike

Re: SEMC SRAM Interface Questions

Hui_Ma — Fri, 01 Feb 2019 07:58:03 GMT

Hi,

SEMC_CSX[0], SEMC_CSX[1], SEMC_CSX[2], and SEMC_CSX[3] has the same function with SEMC_ADD
R[8] pin. It add more flexible for pin selection during SRAM circuit design.

Thank you for the attention.

Have a great day,
Mike