Random Values in Shared OC RAM DualCore

Flo1989 — Fri, 30 Sep 2022 07:27:15 GMT

Hi,

we have a problem with shared OC RAM of the iMXRT1176.

We use MCUXpresso v11.6.0 and SDK Version 2.12.0.

In MCUXpresso we have a Memory Section declared which holds Signals. The CM7 has read/write Access and the CM4 Read Only.

In BoardConfigMPU of CM7 we configure the Section:

extern uint32_t __base_SRAM_OC_Signals; extern uint32_t __top_SRAM_OC_Signals; uint32_t nonCacheSignalsStart = (uint32_t)(&__base_SRAM_OC_Signals); uint32_t SignalsSize = (uint32_t)(&__top_SRAM_OC_Signals) - nonCacheSignalsStart; int i = 0; while ((SignalsSize >> i) > 0x1U) { i++; } if (i != 0) { /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ assert(!(nonCacheSignalsStart % SignalsSize)); assert(SignalsSize == (uint32_t)(1 << i)); assert(i >= 5); /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ MPU->RBAR = ARM_MPU_RBAR(12, nonCacheSignalsStart); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_PRIV, 0, 1, 0, 0, 0, i - 1); }

and in CM4 BoardConfigMPU:

extern uint32_t __base_SRAM_OC_Signals; extern uint32_t __top_SRAM_OC_Signals; uint32_t nonCacheSignalsStart = (uint32_t)(&__base_SRAM_OC_Signals); uint32_t SignalsSize = (uint32_t)(&__top_SRAM_OC_Signals) - nonCacheSignalsStart; int i = 0; while ((SignalsSize >> i) > 0x1U) { i++; } if (i != 0) { /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ assert(!(nonCacheSignalsStart % SignalsSize)); assert(SignalsSize == (uint32_t)(1 << i)); assert(i >= 5); /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ MPU->RBAR = ARM_MPU_RBAR(3, nonCacheSignalsStart); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 1, 0, 0, 0, i - 1); }

On our Architecture we have a custom Bootloader, which executes first. Loads the CM7 and CM4 Images into ITC RAMs of the Cores and jumps to CM7 Core ResetISR().

The CM7 Core then Starts the CM4 Core via MCMGR.

On both Cores FreeRTOS is running, and we implemented a Software Reset over WatchDog, called form CM4 core.

void APP_GlobalSystemReset(void) { wdog_config_t config; /* * wdogConfig->enableWdog = true; * wdogConfig->workMode.enableWait = true; * wdogConfig->workMode.enableStop = false; * wdogConfig->workMode.enableDebug = false; * wdogConfig->enableInterrupt = false; * wdogConfig->enablePowerdown = false; * wdogConfig->resetExtension = flase; * wdogConfig->timeoutValue = 0xFFU; * wdogConfig->interruptTimeValue = 0x04u; */ WDOG_GetDefaultConfig(&config); config.timeoutValue = 0x0U; /* Timeout value is (0x2 + 1)/2 = 0.5 sec. */ WDOG_Init(BOOT_WDOG_BASE, &config); while (1) { } }

If we have an Power On Reset the Application Starts and we have some Random Values in the OC_RAM of the Signals. Both Cores read the Random Values.

When we perform the Software Reset, the Values in the RAM are OK.

The problem occures also when i make a Debug session, where the custom Bootloader has no affect.

We have more Shared Sections where this doesn't happens.

Has anyone a solution for this problem?

Is there any explanation of this Code Line?

MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_PRIV, 0, 1, 0, 0, 0, i - 1);

Thank you very much!

Florian

Re: Random Values in Shared OC RAM DualCore

jay_heng — Sat, 08 Oct 2022 03:37:45 GMT

You can check ARM Cortex-M Reference Manual - MPU section and CMSIS source mpu_armv7.h to know below setting:

MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_PRIV, 0, 1, 0, 0, 0, i - 1);

Basically, It means the memory region property is Normal type, not shareable, non-cacheable, Access Permission privileged access only

i.MX RT Crossover MCUsのトピックRandom Values in Shared OC RAM DualCore

Random Values in Shared OC RAM DualCore

Re: Random Values in Shared OC RAM DualCore