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    <title>i.MX RT Crossover MCUsのトピックRe: IMXRT SDRAM Performance Issue</title>
    <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-SDRAM-Performance-Issue/m-p/1518102#M21500</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/112870"&gt;@maglash64&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Can you share your testing project.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Jing&lt;/P&gt;</description>
    <pubDate>Wed, 07 Sep 2022 03:15:52 GMT</pubDate>
    <dc:creator>jingpan</dc:creator>
    <dc:date>2022-09-07T03:15:52Z</dc:date>
    <item>
      <title>IMXRT SDRAM Performance Issue</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-SDRAM-Performance-Issue/m-p/1517160#M21476</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have a MIMXRT1160-EVK development board.&lt;/P&gt;&lt;P&gt;I created a demo project to test SDRAM performance, and the read/write performance is quite low.&lt;/P&gt;&lt;P&gt;Here are the parameters for the test.&lt;/P&gt;&lt;P&gt;Below is the SEMC init config&lt;/P&gt;&lt;P&gt;SEMC clock is&amp;nbsp;166.73 Mhz&lt;/P&gt;&lt;P&gt;ARM M7 Clock is 600Mhz&lt;/P&gt;&lt;P&gt;sdramconfig.csxPinMux = kSEMC_MUXCSX0;&lt;BR /&gt;sdramconfig.address = 0x80000000;&lt;BR /&gt;sdramconfig.memsize_kbytes = 2 * 32 * 1024; /* 64MB = 2*32*1024*1KBytes*/&lt;BR /&gt;sdramconfig.portSize = kSEMC_PortSize32Bit; /*two 16-bit SDRAMs make up 32-bit portsize*/&lt;BR /&gt;sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;&lt;BR /&gt;sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;&lt;BR /&gt;sdramconfig.casLatency = kSEMC_LatencyTwo;&lt;BR /&gt;sdramconfig.tPrecharge2Act_Ns = 15; /* tRP 15ns */&lt;BR /&gt;sdramconfig.tAct2ReadWrite_Ns = 15; /* tRCD 15ns */&lt;BR /&gt;sdramconfig.tRefreshRecovery_Ns = 70; /* Use the maximum of the (Trfc , Txsr). */&lt;BR /&gt;sdramconfig.tWriteRecovery_Ns = 2; /* tWR 2ns */&lt;BR /&gt;sdramconfig.tCkeOff_Ns = 42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/&lt;BR /&gt;sdramconfig.tAct2Prechage_Ns = 40; /* tRAS 40ns */&lt;BR /&gt;sdramconfig.tSelfRefRecovery_Ns = 70;&lt;BR /&gt;sdramconfig.tRefresh2Refresh_Ns = 60;&lt;BR /&gt;sdramconfig.tAct2Act_Ns = 2; /* tRC/tRDD 2ns */&lt;BR /&gt;sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);&lt;BR /&gt;sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */&lt;BR /&gt;sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;&lt;BR /&gt;sdramconfig.refreshBurstLen = 1;&lt;BR /&gt;sdramconfig.delayChain = 2;&lt;/P&gt;&lt;P&gt;Below is the MPU configuration: (Caching and Buffering on)&lt;/P&gt;&lt;P&gt;MPU-&amp;gt;RBAR = ARM_MPU_RBAR(9, 0x80000000U);&lt;BR /&gt;MPU-&amp;gt;RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);&lt;/P&gt;&lt;P&gt;DCache and ICache are also enabled.&lt;/P&gt;&lt;P&gt;After running the test which transfers 1MiB from SDRAM to DTCM and back for read, these are the results that I got:&lt;/P&gt;&lt;P&gt;starting memtest!&lt;BR /&gt;write data..!&lt;BR /&gt;time for dtcm to sdram write: 7 ms bandwidth: 149.796571 MB/s&lt;BR /&gt;read data..!&lt;BR /&gt;time for sdram to dtcm read: 14 ms bandwidth: 74.898286 MB/s&lt;BR /&gt;time for sdram to sdram copy: 17 ms&lt;/P&gt;&lt;P&gt;This is far cry from what NXP application note AN12437 lists&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="maglash64_0-1662306320840.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/192390iD524434D93BA64F2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="maglash64_0-1662306320840.png" alt="maglash64_0-1662306320840.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Here the write speed is over 320MBps and read is 111MBps.&lt;/P&gt;&lt;P&gt;How it this possible/achieved?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 05 Sep 2022 15:25:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-SDRAM-Performance-Issue/m-p/1517160#M21476</guid>
      <dc:creator>maglash64</dc:creator>
      <dc:date>2022-09-05T15:25:18Z</dc:date>
    </item>
    <item>
      <title>Re: IMXRT SDRAM Performance Issue</title>
      <link>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-SDRAM-Performance-Issue/m-p/1518102#M21500</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/112870"&gt;@maglash64&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Can you share your testing project.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Jing&lt;/P&gt;</description>
      <pubDate>Wed, 07 Sep 2022 03:15:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMXRT-SDRAM-Performance-Issue/m-p/1518102#M21500</guid>
      <dc:creator>jingpan</dc:creator>
      <dc:date>2022-09-07T03:15:52Z</dc:date>
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