topic Re: RT1064: SAI settings in i.MX RT Crossover MCUs

RT1064: SAI settings

mrecoskie — Mon, 06 Jun 2022 14:14:24 GMT

Hi,

I am settings up an audio codec (TI3106) as master to the SAI bus on the RT1064. The protocol being used is DSP mode. I am using the 'sai_edma_transfer' sample - with modification for codec integration.

While I am able to transmit bits, it seems as though the audio samples sent are missing a zero to start. I have tried several SAI settings to correct this but I am unable to make this work.

For example, the sample code starts sending 0x2f, 0x2f. Below is a trace from a logic analyzer. If there was an additional zero at the front of each sample (or a shift) the data would be correct.

For reference the expected format for the TI audio codec is the following:

Any insight is appreciated. Thanks,

Mark

Re: RT1064: SAI settings

kerryzhou — Tue, 07 Jun 2022 07:01:44 GMT

Hi @mrecoskie ,

It should still related to the code configuration and the data sendout.

Please check my doc:

https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/RT10xx-SAI-basic-and-SDCard-wave-file-play/ta-p/1259608

Pic 19

I am using the edma+SAI, and I can sendout the 2ch data correct, the data just put in the C array.

The difference with you just the SYNC bit number, TCR4[SYWD].

So you can try my doc attached project, and change the music array to your data, eg, you want to sendout 0X002F,0X002F, you can set:

_ALIGN_BEGIN const uint8_t music[] __ALIGN_END =
#endif
#endif
{
0x2f, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,..

}

After it can output the correct data, then you can change the TCR4[SYWD]=0, for one bit clock.

Please try it!

If you still have the issues, just debug the code, and share me all your SAI register data, and the related SAI wave.

Wish it helps you!

Best Regards,

kerry

Re: RT1064: SAI settings

mrecoskie — Tue, 07 Jun 2022 20:42:18 GMT

Hi,

The document is very good and this scenario is working.

I believe the difference in my case is the fact that the SAI interface is acting as a Slave to the TI audio codec.

My unique changes include:

saiConfig.masterSlave = kSAI_Slave

saiConfig.bitclock.bclkSrcSwap = true

The IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK bit is removed.

The bus clock of the RT1064 is internal 12.288. The BCLK/WCLK is externally generated.

The data sent through DMA is confirmed correct. I feel there must be some data misalignment however it is difficult to see what is happening.

In the case of operating the SAI interface as a slave, what settings should be checked? Thanks.

Re: RT1064: SAI settings

kerryzhou — Wed, 08 Jun 2022 03:15:32 GMT

Hi @mrecoskie ，

Thanks a lot for your effort.

So, your TI codec is master, the MCLK is from RT1064, then SYNC, BCLK are all from TI codec to RT1064, right?

I mean, the master connection like the following:

So, now, the data from slave TX to master RX, find the misalignment, right?

Please debug your code, check this register:

TCR4[FSE], whether it is 0, or 1?

You can share all the TCSR, and TCR1-TCR5 data, just check the configuration, and whether there are some clues or not.

What's the BCLK clock frequency now?

Just make sure the clock is not larger than the datasheet's data.

Also make sure your SAI root clock higher than BCLK, that's should be good.

Best Regards,

Kerry

Re: RT1064: SAI settings

mrecoskie — Wed, 08 Jun 2022 19:15:01 GMT

Hi Kerry,

Thank you for the help.

Yes. The TI codec is master. The MCLK is set as input to the RT1064. However the plan is to remove the MCLK physical line in the final design. Will this be a problem for the RT1064? The SYNC and BCLK are from the TI codec. Correct.

Yes. The data from the slave TX to the master RX is not good.

The TCR4[FSE] is 0 however I have tried varying this setting to 1 also.

TCSR, TCR1 -TCR5 values are listed below.

TCSR = 0x00000400

TCR1 = 0x00000010

TCR2 = 0x24000003

TCR3 = 0x00000000

TCR4 = 0x10010038

TCR5 = 0x0F0F0F00

The BCLK frequency is 657 kHz. The SAI root clock is set to 12.288MHz

Mark

Re: RT1064: SAI settings

kerryzhou — Thu, 09 Jun 2022 04:24:58 GMT

Hi @mrecoskie ,

If the TI can send out the clock by itself without the external MCLK, it's also to the RT1064 receive the BCLK and SYNC.

Please check your code, set the TCR4[FSE]=0.

As, I find your data set FSE =1.

Then test the wave again, whether that have any improvement or not?

Best Regards,

Kerry

Re: RT1064: SAI settings

mrecoskie — Fri, 10 Jun 2022 01:38:26 GMT

Hi Kerry,

TCR4[FSE]=0 is no improvement.

Do you have a tested example of this configuration?

Thanks.

Mark

Re: RT1064: SAI settings

kerryzhou — Fri, 10 Jun 2022 02:33:14 GMT

Hi @mrecoskie ,

In fact, I don't have your TI codec, so I didn't test it like that.

I normally test it which I told you, and another test, one RT as master, another as slave. The wave like this:

The connection is:

You can see my slave TX data is also correct, no shift.

I also attach my slave code for your reference, and a doc, but I am write it in chinese, you can just check the pictures.

My understand is, your situation is similar, just the channel, and SYNC width has difference.

Re: RT1064: SAI settings

mrecoskie — Mon, 13 Jun 2022 15:49:09 GMT

Thank you Kerry. I reviewed the code but I see the lines:

BOARD_EnableSaiMclkOutput(true);

and

saiConfig.bitclock.bclkSrcSwap not set to true

Are you sure the clocks are slave by evkbimxrt1050_sai2_edma_record_playback_48K32bit_sync ?

I don’t understand how this is possible with these settings.

Also I noticed you are using SAI2. Can SAI1 be used or is there a limitation with this interface?

Thanks.

Mark

Re: RT1064: SAI settings

kerryzhou — Tue, 14 Jun 2022 02:55:28 GMT

Hi @mrecoskie ,

Good question!

You can check the above reply, the block connection picture.

In fact, the MCLK didn't connect to the master side.

So, you don't need to care about it, as I modify the code based on the SDK, the SDK enable it, but I am using the SAI2, you just need to care about the SAI2 configuration is OK, this MCLK won't influence slave function.

Best Regards,

kerry

Re: RT1064: SAI settings

mrecoskie — Tue, 14 Jun 2022 03:10:34 GMT

Makes sense. What about setting the BCLK direction?

Re: RT1064: SAI settings

kerryzhou — Tue, 14 Jun 2022 03:23:25 GMT

Hi @mrecoskie ，

https://community.nxp.com/t5/image/serverpage/image-id/182923i0D3F4715A8AB84AF/image-size/medium?v=v2&px=400

The above picture already indicate it, to slave, BCLK is input, to master, BCLK is output.

Best Regards,

kerry

Re: RT1064: SAI settings

mrecoskie — Tue, 14 Jun 2022 03:35:21 GMT

Hi Kerry,

I see the picture but in the slave code shouldn't the bclk direction be set - specifically the 'config->bitClock.bclkSrcSwap' variable? I don't see this set to 'true'.

Thanks.

Mark

Re: RT1064: SAI settings

kerryzhou — Tue, 14 Jun 2022 04:20:54 GMT

Hi @mrecoskie ,

Check the driver code, you will be clear:

When it is slave:

saiConfig.masterSlave = kSAI_Slave

Even you set config->bitClock.bclkSrcSwap, it won't be configure the real register.

Wish it helps you!

Best Regards,

Kerry

Re: RT1064: SAI settings

mrecoskie — Thu, 14 Jul 2022 15:59:53 GMT

To confirm - in your diagram TXBCLK is connected to TXBCLK between the master and slave. Is this correct?

The hardware connections should be the following??

Master.       Slave.

MCLK.     <—> MCLK

TXSYNC    <—> TXSYNC

TXBCLK.   <—> TXBCLK

TXDATA    ——> RXDATA

RXDATA    <—- TXDATA

Re: RT1064: SAI settings

kerryzhou — Fri, 15 Jul 2022 05:01:31 GMT

Hi @mrecoskie ，

MCLK is not must to connect, others is correct!

BTW, this post is really very old, more than one month, if you have any issues, please help to create the new question post, thanks. Don't update the old post.

Best Regards,

Kerry

Re: RT1064: SAI settings

mrecoskie — Mon, 18 Jul 2022 13:17:28 GMT

Hi Kerry,

Final question - is it possible TXBCLK (master) connected to RXBCLK (slave) also works??

Mark

Re: RT1064: SAI settings

kerryzhou — Mon, 18 Jul 2022 22:27:08 GMT

Hi @mrecoskie ,

It is determined by your slave Synchronous mode, you can find it from the RM:

As this case is very old, more than one month, if you have any question or updated information, please help to create the new question post, we also can help you in the new question post, thanks.

Best Regards,

kerry