topic Re: RT1176 - GPIO13 port timing seem to be much lower performance than GPIO3 in i.MX RT Crossover MCUs

RT1176 - GPIO13 port timing seem to be much lower performance than GPIO3

JRIIS — Mon, 30 May 2022 11:33:02 GMT

customer - MUSIC Tribe Brands DK - have a problem with the i.MX RT1176 chip regarding GPIO timing/performance.

When they use the GPIO13 port, some simple operations as setting and clearing a GPIO pin takes a lot
more time than if they do the same operation on a GPIO pin on GPIO3 port.
When they use a pin on GPIO3 the time for setting and clearing a GPIO pin is app. 80 ns
for both setting and clearing. (As accurate as it can be measured with the analyzer
running 32 M samples/s)
When they use a pin on GPIO13 the time for setting and clearing a GPIO pin is app. 185 us
for both setting and clearing. It seems like the cpu is stalled for this amount of
time every time a GPIO register is accessed on GPIO13
The simple test routine shown below is executed before any interrupts are enabled and
before the FreeRTOS scheduling is started.
The code is located in ITCM memory
The Cortex M7 core root clock is 996 MHz.
The Bus clock root is 240 Mhz.
The Bus LPSR clock root is 160 MHz.
I have the .mex file it can be delivered on request since I where not able to attach it below.

/Jakob

Re: RT1176 - GPIO13 port timing seem to be much lower performance than GPIO3

Masmiseim — Mon, 30 May 2022 13:31:41 GMT

Hello JRIIS,

GPIO13 is part of the SVNS Domain. Accessing the GPIO is done via AIPS4 of the XB which is really slow. The Bus is running with 32 KHz only. This is done to keep the SNVS Domain below 5 uA in deep-sleep.

So, the behavior you see is working as intended.

Regards

Re: RT1176 - GPIO13 port timing seem to be much lower performance than GPIO3

JRIIS — Mon, 30 May 2022 14:09:28 GMT

Hello Masmiseim,

Thanks for fast and clear replay.

I will discuss with SE to get discussion if documentation could be better.

Thanks,

/Jakob