https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SDRAM-ECC/m-p/1437336#M18967 <P>eFUSE 0x840[3] bit should be burnt to enable XECC module, or XECC is inactive by default.</P> <P>See my blog for XECC enablement.</P> <P><A href="https://www.cnblogs.com/henjay724/p/15204125.html" target="_blank">https://www.cnblogs.com/henjay724/p/15204125.html</A></P> Fri, 01 Apr 2022 03:17:50 GMT jay_heng 2022-04-01T03:17:50Z https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SDRAM-ECC/m-p/1434624#M18915 <P>Hello teams.</P><P>We designed an i.MX RT1171 custom board and connect it to the SDRAM on the SEMC bus.<BR />Please tell us how to enable ECC.</P><P>We enabled XECC_SEMC[ECC_CTRL] bit2-0 and address settings, but it doesn't work.<BR />Must be set to the eFUSE 0x840[3] bit?<BR />Is there any other settings ?</P><P>Best regards.</P> Mon, 28 Mar 2022 23:57:50 GMT https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SDRAM-ECC/m-p/1434624#M18915 Ootsuka 2022-03-28T23:57:50Z https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SDRAM-ECC/m-p/1437336#M18967 <P>eFUSE 0x840[3] bit should be burnt to enable XECC module, or XECC is inactive by default.</P> <P>See my blog for XECC enablement.</P> <P><A href="https://www.cnblogs.com/henjay724/p/15204125.html" target="_blank">https://www.cnblogs.com/henjay724/p/15204125.html</A></P> Fri, 01 Apr 2022 03:17:50 GMT https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SDRAM-ECC/m-p/1437336#M18967 jay_heng 2022-04-01T03:17:50Z https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SDRAM-ECC/m-p/1437373#M18972 <P>Thank you very much for answer.</P> Fri, 01 Apr 2022 03:56:59 GMT https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/SDRAM-ECC/m-p/1437373#M18972 Ootsuka 2022-04-01T03:56:59Z